Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide

More documents

Recommendations

Info

Chapter 1: Introduction to the RocketIO GTX TransceiverTable 1-3:GTX_DUAL Port Summary (Cont’d)Port Dir Domain Description Section (Page)INTDATAWIDTH In AsyncSets the internal datapath widthfor the GTX_DUAL tile.0: 16-bit internal datapathwidth1: 20-bit internal datapathwidthShared PMA PLL (page 87),FPGA TX Interface(page 120),Parallel In to Serial Out(page 149), Serial In toParallel Out (page 183),PRBS Detection (page 190),Configurable RX ElasticBuffer and Phase Alignment(page 205), ConfigurableClock Correction (page 212),Configurable ChannelBonding (Lane Deskew)(page 219), FPGA RXInterface (page 236)LOOPBACK0[2:0]LOOPBACK1[2:0]In Async Sets the loopback mode. Loopback (page 250)PHYSTATUS0PHYSTATUS1OutAsyncIndicates completion of severalPHY functions, including powermanagement state transitionsand receiver detection.Receive Detect Support forPCI Express Operation(page 154)PLLLKDET Out AsyncIndicates that the VCO rate iswithin acceptable tolerances ofthe desired rate.Shared PMA PLL (page 87)PLLLKDETEN In Async Enables the PLL lock detector. Shared PMA PLL (page 87)PLLPOWERDOWN In AsyncPowers down the shared PMAPLL.Power Control (page 110)PRBSCNTRESET0PRBSCNTRESET1In RXUSRCLK2 Resets the PRBS error counter. PRBS Detection (page 190)REFCLKOUT Out N/AREFCLKPWRDNB In AsyncProvides access to the referenceclock provided to the sharedPMA PLL (CLKIN).Powers down the GTX referenceclock circuit (active Low).Shared PMA PLL (page 87),Clocking (page 98), FPGATX Interface (page 120), TXBuffering, Phase Alignment,and TX Skew Reduction(page 143),FPGA RX Interface(page 236)Power Control (page 110)RESETDONE0RESETDONE1OutAsyncIndicates when the GTXtransceiver has finished reset andis ready for use.Reset (page 102), RX ClockData Recovery (page 179)32 www.xilinx.com RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Ports and AttributesTable 1-3:GTX_DUAL Port Summary (Cont’d)Port Dir Domain Description Section (Page)RXBUFRESET0RXBUFRESET1In Async Resets the RX elastic buffer logic.Reset (page 102),Configurable RX ElasticBuffer and Phase Alignment(page 205),Configurable ClockCorrection (page 212)RXBUFSTATUS0[2:0]RXBUFSTATUS1[2:0]OutRXUSRCLK2Indicates theoverflow/underflow status ofthe RX elastic buffer.Configurable RX ElasticBuffer and Phase Alignment(page 205),Configurable ClockCorrection (page 212)RXBYTEISALIGNED0RXBYTEISALIGNED1OutRXUSRCLK2Indicates if the parallel datastream is properly aligned onbyte boundaries according tocomma detection.WhenPCOMMA_ALIGN = TRUE,asserted for alignment toPCOMMA value. WhenMCOMMA_ALIGN = TRUE,asserted for alignment toMCOMMA value.Configurable CommaAlignment and Detection(page 192)RXBYTEREALIGN0RXBYTEREALIGN1OutRXUSRCLK2Indicates if the byte alignmentwithin the serial data stream haschanged due to a commadetection.Configurable CommaAlignment and Detection(page 192)RXCDRRESET0RXCDRRESET1InRXUSRCLK2Reset for the RX CDR. Also resetsthe rest of the RX PCS.Reset (page 102),RX Clock Data Recovery(page 179)RXCHANBONDSEQ0RXCHANBONDSEQ1OutRXUSRCLK2Indicates when RXDATAcontains the start of a channelbonding sequence.Configurable ChannelBonding (Lane Deskew)(page 219)RXCHANISALIGNED0RXCHANISALIGNED1OutRXUSRCLK2Indicates if the channel isproperly aligned with the mastertransceiver according toobserved channel bondingsequences in the data stream.Configurable ChannelBonding (Lane Deskew)(page 219)RXCHANREALIGN0RXCHANREALIGN1OutRXUSRCLK2Held High for at least one cyclewhen the receiver has changed.Configurable ChannelBonding (Lane Deskew)(page 219)RocketIO GTX Transceiver User Guide www.xilinx.com 33UG198 (v3.0) October 30, 2009
Page 1: Virtex-5 FPGARocketIO GTXTransceive
Page 6 and 7: RocketIO GTX Transceiver User Guide
Page 8 and 9: Chapter 4: ImplementationOverview .
Page 10: TX PRBS Generator . . . . . . . . .
Page 18 and 19: Preface: About This GuideAdditional
Page 20 and 21: Preface: About This GuideTypographi
Page 22 and 23: Section 1: FPGA Level Design22 www.
Page 24 and 25: Chapter 1: Introduction to the Rock
Page 52 and 53: Chapter 2: RocketIO GTX Transceiver
Page 54 and 55: Chapter 3: SimulationPorts and Attr
Page 56 and 57: Chapter 3: Simulationphased out aft
Page 58 and 59: Chapter 3: SimulationO : out std_lo
Page 60 and 61: Chapter 3: SimulationExample for PC
Page 62 and 63: Chapter 4: ImplementationTable 4-1:
Page 64 and 65: Chapter 4: ImplementationPackage Pl
Page 66 and 67: Chapter 4: ImplementationX-Ref Targ
Page 82 and 83:
Chapter 4: ImplementationX-Ref Targ
Page 84 and 85:
Chapter 4: Implementation84 www.xil
Page 86 and 87:
Chapter 5: Tile FeaturesShared PMA
Page 88 and 89:
Chapter 5: Tile FeaturesDescription
Page 90 and 91:
Chapter 5: Tile FeaturesTable 5-3:S
Page 92 and 93:
Chapter 5: Tile FeaturesExamplesCon
Page 94 and 95:
Chapter 5: Tile FeaturesConfiguring
Page 96 and 97:
Chapter 5: Tile FeaturesClockingOve
Page 98 and 99:
Chapter 5: Tile FeaturesPorts and A
Page 100 and 101:
Chapter 5: Tile FeaturesX-Ref Targe
Page 102 and 103:
Page 104 and 105:
Page 106 and 107:
Chapter 5: Tile FeaturesResetting t
Page 108 and 109:
Chapter 5: Tile FeaturesExamplesPow
Page 110 and 111:
Chapter 5: Tile FeaturesPower Contr
Page 112 and 113:
Page 114 and 115:
Chapter 5: Tile FeaturesTable 5-14:
Page 116 and 117:
Page 118 and 119:
Chapter 5: Tile Features118 www.xil
Page 120 and 121:
Chapter 6: GTX Transmitter (TX)FPGA
Page 122 and 123:
Chapter 6: GTX Transmitter (TX)Tabl
Page 124 and 125:
Chapter 6: GTX Transmitter (TX)Conn
Page 126 and 127:
Chapter 6: GTX Transmitter (TX)TXOU
Page 128 and 129:
Chapter 6: GTX Transmitter (TX)REFC
Page 130 and 131:
Chapter 6: GTX Transmitter (TX)Port
Page 132 and 133:
Chapter 6: GTX Transmitter (TX)Desc
Page 134 and 135:
Chapter 6: GTX Transmitter (TX)TX G
Page 136 and 137:
Chapter 6: GTX Transmitter (TX)X-Re
Page 138 and 139:
Chapter 6: GTX Transmitter (TX)Figu
Page 140 and 141:
Page 142 and 143:
Page 144 and 145:
Page 146 and 147:
Page 148 and 149:
Chapter 6: GTX Transmitter (TX)TX P
Page 150 and 151:
Chapter 6: GTX Transmitter (TX)Conf
Page 152 and 153:
Page 154 and 155:
Page 156 and 157:
Chapter 6: GTX Transmitter (TX)Figu
Page 158 and 159:
Page 160 and 161:
Chapter 6: GTX Transmitter (TX)160
Page 162 and 163:
Chapter 7: GTX Receiver (RX)10. “
Page 164 and 165:
Chapter 7: GTX Receiver (RX)Optiona
Page 166 and 167:
Chapter 7: GTX Receiver (RX)X-Ref T
Page 168 and 169:
Chapter 7: GTX Receiver (RX)Table 7
Page 170 and 171:
Chapter 7: GTX Receiver (RX)♦ For
Page 172 and 173:
Chapter 7: GTX Receiver (RX)In most
Page 174 and 175:
Page 176 and 177:
Page 178 and 179:
Page 180 and 181:
Page 182 and 183:
Page 184 and 185:
Page 186 and 187:
Chapter 7: GTX Receiver (RX)Ports a
Page 188 and 189:
Page 190 and 191:
Chapter 7: GTX Receiver (RX)PRBS De
Page 192 and 193:
Page 194 and 195:
Page 196 and 197:
Chapter 7: GTX Receiver (RX)Alignme
Page 198 and 199:
Page 200 and 201:
Chapter 7: GTX Receiver (RX)Configu
Page 202 and 203:
Chapter 7: GTX Receiver (RX)8B/10B
Page 204 and 205:
Page 206 and 207:
Page 208 and 209:
Page 210 and 211:
Chapter 7: GTX Receiver (RX)Bypassi
Page 212 and 213:
Chapter 7: GTX Receiver (RX)Ports a
Page 214 and 215:
Page 216 and 217:
Chapter 7: GTX Receiver (RX)CLK_COR
Page 218 and 219:
Chapter 7: GTX Receiver (RX)Configu
Page 220 and 221:
Page 222 and 223:
Page 224 and 225:
Page 226 and 227:
Page 228 and 229:
Page 230 and 231:
Page 232 and 233:
Page 234 and 235:
Page 236 and 237:
Chapter 7: GTX Receiver (RX)FPGA RX
Page 238 and 239:
Chapter 7: GTX Receiver (RX)Figure
Page 240 and 241:
Chapter 7: GTX Receiver (RX)240 www
Page 242 and 243:
Chapter 8: Cyclic Redundancy CheckX
Page 244 and 245:
Chapter 8: Cyclic Redundancy CheckT
Page 246 and 247:
Chapter 8: Cyclic Redundancy CheckT
Page 248 and 249:
Chapter 8: Cyclic Redundancy Check
Page 250 and 251:
Chapter 9: LoopbackThe LOOPBACK[2:0
Page 252 and 253:
Chapter 9: LoopbackIn the Far-End P
Page 254 and 255:
Chapter 10: GTX-to-Board InterfaceT
Page 256 and 257:
Page 258 and 259:
Page 260 and 261:
Page 262 and 263:
Chapter 10: GTX-to-Board InterfaceX
Page 264 and 265:
Chapter 10: GTX-to-Board InterfaceF
Page 266 and 267:
Chapter 10: GTX-to-Board InterfaceP
Page 268 and 269:
Page 270 and 271:
Page 272 and 273:
Chapter 10: GTX-to-Board InterfaceE
Page 274 and 275:
Page 276 and 277:
Chapter 10: GTX-to-Board InterfaceS
Page 278 and 279:
Chapter 10: GTX-to-Board InterfaceS
Page 280 and 281:
Page 282 and 283:
Chapter 10: GTX-to-Board Interface2
Page 284 and 285:
Section 2: Board Level Design284 ww
Page 286 and 287:
Chapter 11: Design Constraints Over
Page 288 and 289:
Page 290 and 291:
Page 292 and 293:
Page 294 and 295:
Chapter 12: PCB Materials and Trace
Page 296 and 297:
Page 298 and 299:
Page 300 and 301:
Chapter 13: Design of TransitionsX-
Page 302 and 303:
Page 304 and 305:
Page 306 and 307:
Page 308 and 309:
Chapter 13: Design of TransitionsP/
Page 310 and 311:
Page 312 and 313:
Chapter 13: Design of Transitions31
Page 314 and 315:
Chapter 14: Guidelines and Examples
Page 316 and 317:
Chapter 14: Guidelines and Examples
Page 318 and 319:
Section 3: Appendices318 www.xilinx
Page 320 and 321:
Appendix A: MGT to GTX Transceiver
Page 322 and 323:
Page 324 and 325:
Page 326 and 327:
Page 328 and 329:
Page 330 and 331:
Page 332 and 333:
Appendix B: OOB/Beacon SignalingX-R
Page 334 and 335:
Appendix C: 8B/10B Valid Characters
Page 336 and 337:
Page 338 and 339:
Page 340 and 341:
Page 342 and 343:
Page 344 and 345:
Appendix D: DRP Address Map of the
Page 346 and 347:
Page 348 and 349:
Page 350 and 351:
Page 352 and 353:
Page 354 and 355:
Page 356 and 357:
Page 358 and 359:
Page 360 and 361:
Page 362 and 363:
Page 364 and 365:
Page 366 and 367:
Page 368 and 369:
368 www.xilinx.com RocketIO GTX Tra
Page 370 and 371:
Page 372 and 373:
Page 374 and 375:
Page 376 and 377:
Appendix E: Low Latency DesignGTX T
Page 378 and 379:
Appendix E: Low Latency Design378 w
Page 380 and 381:
Appendix F: Advanced ClockingX-Ref
Page 382 and 383:
Appendix F: Advanced ClockingTable
Page 384 and 385:
Infiniband 245PCI Express 245SATA 2
Page 386 and 387:
TX PISO 149TX polarity control 147T
show all

Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?