Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide

OverviewX-Ref Target - Figure 1-2GTX_DUALX0 ColumnVirtex-5 FPGA (XC5VTX150T)GTX_DUALX1 ColumnGTX_DUALX0_Y9CRCBlocksCRCBlocksGTX_DUALX1_Y9GTX_DUALX0_Y8CRCBlocksCRCBlocksGTX_DUALX1_Y8GTX_DUALX0_Y7CRCBlocksCRCBlocksGTX_DUALX1_Y7GTX_DUALX0_Y6CRCBlocksCMTCRCBlocksGTX_DUALX1_Y6GTX_DUALX0_Y5CRCBlocksCMTCMTEthernetMACCRCBlocksGTX_DUALX1_Y5GTX_DUALX0_Y4CRCBlocksI/OColumnConfigurationandClockI/OColumnEthernetMACCRCBlocksGTX_DUALX1_Y4GTX_DUALX0_Y3CRCBlocksCRCBlocksGTX_DUALX1_Y3GTX_DUALX0_Y2CRCBlocksCMTCMTIntegratedBlock forPCI ExpressOperationCRCBlocksGTX_DUALX1_Y2GTX_DUALX0_Y1CRCBlocksCMTCRCBlocksGTX_DUALX1_Y1GTX_DUALX0_Y0CRCBlocksCRCBlocksGTX_DUALX1_Y0UG198_c1_03_071508Notes:1. This figure does not illustrate exact size, location, or scale of the functional blocks to each other. It does show the correct number of availableresources.2. To improve clarity, this figure does not show the CLB, DSP, and block RAM columns.3. Channel bonding of multiple transceivers in different columns is an advanced feature. Contact your System I/O specialist for details.4. GTX_DUAL tiles of column X1 must be used when connecting to the Ethernet MAC blocks or to the Integrated Block for PCI Expressoperation.Figure 1-2:GTX_DUAL Tile Inside the Virtex-5 XC5VTX150T FPGARocketIO GTX Transceiver User Guide www.xilinx.com 27UG198 (v3.0) October 30, 2009