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Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide

Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide

Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide

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Ports and AttributesTable 1-3:<strong>GTX</strong>_DUAL Port Summary (Cont’d)Port Dir Domain Description Section (Page)RXENEQB0RXENEQB1InAsyncThis port has no effect ontransceiver performance.–RXENMCOMMAALIGN0RXENMCOMMAALIGN1InRXUSRCLK2Aligns the byte boundary whencomma minus is detected.Configurable CommaAlignment and Detection(page 192)RXENPCOMMAALIGN0RXENPCOMMAALIGN1InRXUSRCLK2Aligns the byte boundary whencomma plus is detected.Configurable CommaAlignment and Detection(page 193)RXENPMAPHASEALIGN0RXENPMAPHASEALIGN1InRXUSRCLK2Enables the alignment of theXCLK with the RXURSCLK(independently) for eachtransceiver in the <strong>GTX</strong>_DUALtile. Set High when bypassing theRX elastic buffer.Configurable RX ElasticBuffer and Phase Alignment(page 205)RXENPRBSTST0[1:0]RXENPRBSTST1[1:0]InRXUSRCLK2Receiver test pattern checkercontrol.PRBS Detection (page 190)RXENSAMPLEALIGN0RXENSAMPLEALIGN1InRXUSRCLK2When High, the 5x oversamplerin the PCS continually adjusts itssample point. When Low, itsamples only at the point thatwas active before the port wentLow.Oversampling (page 186)RXEQMIX0[1:0]RXEQMIX1[1:0]InAsyncSets the wideband/high-passmix ratio for the RX equalizer.RX Termination andEqualization (page 162)RXGEARBOXSLIP0RXGEARBOXSLIP1InRXUSRCLK2Slips the RX Gearbox position byone cycle.RX Gearbox (page 231)RXHEADER0[2:0]RXHEADER1[2:0]Out RXUSRCLK2 RX header bits from RX Gearbox. RX Gearbox (page 231)RXHEADERVALID0RXHEADERVALID1OutRXUSRCLK2Indicates when RX header bitsfrom the RX Gearbox are valid.RX Gearbox (page 231)RXLOSSOFSYNC0[1:0]RXLOSSOFSYNC1[1:0]OutRXUSRCLK2<strong>FPGA</strong> status related to bytestream synchronization,depending on the state of theRX_LOSS_OF_SYNC_FSMattribute.Configurable Loss-of-SyncState Machine (page 197)RXNOTINTABLE0[3:0]RXNOTINTABLE1[3:0]OutRXUSRCLK2Indicates if RXDATA is the resultof an 8B/10B code that is in error.Configurable 8B/10BDecoder (page 201)RXOVERSAMPLEERR0RXOVERSAMPLEERR1OutRXUSRCLK2Indicates the FIFO inoversampling circuit has eitheroverflowed or underflowed.Oversampling (page 186)<strong>RocketIO</strong> <strong>GTX</strong> <strong>Transceiver</strong> <strong>User</strong> <strong>Guide</strong> www.xilinx.com 35<strong>UG198</strong> (v3.0) October 30, 2009

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