Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide

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Chapter 1: Introduction to the RocketIO GTX TransceiverTable 1-5:GTX_DUAL Attribute Summary (Cont’d)Attribute Type Description Section (Page)RX_EN_IDLE_HOLD_DFE_0RX_EN_IDLE_HOLD_DFE_1BooleanWhen TRUE, restores the DFE contentsfrom internal registers aftertermination of an electrical idle statefor PCI Express designs.Reset (page 103), DecisionFeedback Equalization(page 168)RX_EN_IDLE_RESET_BUF_0RX_EN_IDLE_RESET_BUF_1BooleanWhen TRUE, and no valid signal ispresent at the RX inputs, resets the RXelastic buffer.Reset (page 103),Configurable RX ElasticBuffer and PhaseAlignment (page 206)RX_EN_IDLE_RESET_FRBooleanWhen TRUE, enables the reset of theCDR frequency circuits by using anoptional reset sequence while in anelectrical idle state for PCI Expressdesigns.Reset (page 103), RX ClockData Recovery (page 180)RX_EN_IDLE_RESET_PHBooleanWhen TRUE, enables the reset of theCDR phase circuits by using anoptional reset sequence while in anelectrical idle state for PCI Expressdesigns.Reset (page 103), RX ClockData Recovery (page 180)RX_IDLE_HI_CNT_0RX_IDLE_HI_CNT_14-bitBinaryDetermines how long valid data on theRX inputs must be absent beforeasserting the reset signal to the RXelastic buffer.Reset (page 103),Configurable RX ElasticBuffer and PhaseAlignment (page 206)RX_IDLE_LO_CNT_0RX_IDLE_LO_CNT_14-bitBinaryDetermines how long valid data on theRX inputs must be present beforedeasserting the reset signal to the RXelastic buffer.Reset (page 103),Configurable RX ElasticBuffer and PhaseAlignment (page 206)RX_LOS_INVALID_INCR_0RX_LOS_INVALID_INCR_1IntegerDefines the number of valid charactersrequired to decrement the error countby 1 for the purpose of loss-of-syncdetermination.Configurable Loss-of-SyncState Machine (page 198)RX_LOS_THRESHOLD_0RX_LOS_THRESHOLD_1IntegerDefines the error count required tomove the Loss of Sync state machinefrom the SYNC_ACQUIRED to theSYNC_LOST state.Configurable Loss-of-SyncState Machine (page 198)RX_LOSS_OF_SYNC_FSM_0RX_LOSS_OF_SYNC_FSM_1BooleanDefines the behavior of theRXLOSSOFSYNC outputs.Configurable Loss-of-SyncState Machine (page 198)RX_SLIDE_MODE_0RX_SLIDE_MODE_1StringSelects between sliding in the PMA orin the PCS.Configurable CommaAlignment and Detection(page 194)RX_STATUS_FMT_0RX_STATUS_FMT_1StringSets whether the RX_STATUS port isused to report the status of PCI Expressor SATA features.RX OOB/Beacon Signaling(page 175)46 www.xilinx.com RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Ports and AttributesTable 1-5:GTX_DUAL Attribute Summary (Cont’d)Attribute Type Description Section (Page)RX_XCLK_SEL_0RX_XCLK_SEL_1StringSelects which clock is used on the PMAside of the RX elastic buffer. Thedefault setting is RXREC (RXrecovered clock). Use RXUSR(RXUSRCLK) when bypassing the RXelastic buffer.Configurable RX ElasticBuffer and PhaseAlignment (page 206)RXGEARBOX_USE_0RXGEARBOX_USE_1Boolean Enables the RX Gearbox. RX Gearbox (page 232)SATA_BURST_VAL_0SATA_BURST_VAL_13-bitBinaryNumber of bursts required for theSATA OOB detector to declare a COMmatch.RX OOB/Beacon Signaling(page 175)SATA_IDLE_VAL_0SATA_IDLE_VAL_13-bitBinaryNumber of idles required for the SATAOOB detector to declare a COM match.RX OOB/Beacon Signaling(page 175)SATA_MAX_BURST_0SATA_MAX_BURST_1IntegerSets the threshold for the SATAdetector to reject a burst in terms ofsquelch clock cycles.RX OOB/Beacon Signaling(page 175)SATA_MAX_INIT_0SATA_MAX_INIT_1IntegerSets the maximum time allowed for aCOMINIT/COMRESET idle for theSATA detector in terms of squelchclock cycles.RX OOB/Beacon Signaling(page 175)SATA_MAX_WAKE_0SATA_MAX_WAKE_1IntegerSets the maximum time allowed for aCOMWAKE idle for the SATA detectorin terms of squelch clock cycles.RX OOB/Beacon Signaling(page 175)SATA_MIN_BURST_0SATA_MIN_BURST_1IntegerSets the threshold for the SATAdetector to reject a burst in terms ofsquelch clock cycles.RX OOB/Beacon Signaling(page 176)SATA_MIN_INIT_0SATA_MIN_INIT_1IntegerSets the minimum time allowed for aCOMINIT/COMRESET idle for theSATA detector in terms of squelchclock cycles.RX OOB/Beacon Signaling(page 176)SATA_MIN_WAKE_0SATA_MIN_WAKE_1IntegerSets the minimum time allowed for aCOMWAKE idle for the SATA detectorin terms of squelch clock cycles.RX OOB/Beacon Signaling(page 176)SIM_GTXRESET_SPEEDUPIntegerShortens the time it takes to finish theGTXRESET sequence and PLL lockduring simulation.Simulation (page 54)SIM_MODEStringThis simulation-only attribute choosesbetween FAST and LEGACYsimulation models.Simulation (page 54)SIM_PLL_PERDIV2 9-bit HexSpecifies the length of one symbol inpicoseconds for simulation.Simulation (page 54)SIM_RECEIVER_DETECT_PASS0SIM_RECEIVER_DETECT_PASS1BooleanControls the receiver detect modelingin simulation and is intended for PCIExpress designs only.Simulation (page 54)RocketIO GTX Transceiver User Guide www.xilinx.com 47UG198 (v3.0) October 30, 2009
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Appendix A: MGT to GTX Transceiver
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Infiniband 245PCI Express 245SATA 2
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TX PISO 149TX polarity control 147T
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Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide

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