Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide

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Chapter 1: Introduction to the RocketIO GTX TransceiverTable 1-4:CRC Port Summary (Cont’d)Port Dir Domain Description Section (Page)CRCIN[63:0] In CRCCLKCRCOUT[31:0] Out CRCCLKCRCRESET In CRCCLKCRC input data. The maximumdatapath width is eight bytes.32-bit CRC output. CRCOUT isthe byte-reversed, bit-invertedCRC value corresponding to theCRC calculation on valid bytesfrom the previous clock cycleand the previous CRC value.CRCDATAVALIDA must bedriven High.Synchronous reset of CRCregisters.Cyclic Redundancy Check(page 242)Cyclic Redundancy Check(page 242)Cyclic Redundancy Check(page 242)Table 1-5 lists alphabetically the attribute names, default values, and directions of theGTX_DUAL attributes, and provides links to their detailed descriptions.Table 1-5:GTX_DUAL Attribute SummaryAttribute Type Description Section (Page)AC_CAP_DIS_0AC_CAP_DIS_1BooleanDisables built-in AC couplingcapacitors on receiver inputs when setto TRUE.RX Termination andEqualization (page 163)ALIGN_COMMA_WORD_0ALIGN_COMMA_WORD_1IntegerControls alignment of detectedcommas within a multi-byte datapath.Configurable CommaAlignment and Detection(page 193)CB2_INH_CC_PERIOD_0CB2_INH_CC_PERIOD_1IntegerSpecific for PCI Express designs,allows removal or retaining of controlcharacters during channel bondingand clock correction.Configurable ChannelBonding (Lane Deskew)(page 219)CDR_PH_ADJ_TIME5-bitBinaryDefines the waiting time afterdeassertion of the CDR phase resetbefore the optional reset sequence forPCI Express designs is completeduring electrical idle.Reset (page 103), RX ClockData Recovery (page 179)CHAN_BOND_1_MAX_SKEW_0CHAN_BOND_1_MAX_SKEW_1CHAN_BOND_2_MAX_SKEW_0CHAN_BOND_2_MAX_SKEW_1IntegerSets the maximum amount of laneskew allowed when using channelbonding. Must be set less than one-halfthe minimum distance betweenchannel bonding sequences.Configurable ChannelBonding (Lane Deskew)(page 219)CHAN_BOND_KEEP_ALIGN_0CHAN_BOND_KEEP_ALIGN_1BooleanSpecific for PCI Express designs,allows lanes to remember the previousskew during periods of electrical idle.Configurable ChannelBonding (Lane Deskew)(page 219)CHAN_BOND_LEVEL_0CHAN_BOND_LEVEL_1IntegerIndicates the amount of internalpipelining used for the elastic buffercontrol signals.Configurable ChannelBonding (Lane Deskew)(page 220)40 www.xilinx.com RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Ports and AttributesTable 1-5:GTX_DUAL Attribute Summary (Cont’d)Attribute Type Description Section (Page)CHAN_BOND_MODE_0CHAN_BOND_MODE_1StringDefines the channel bonding mode ofoperation for the transceiver.Configurable ChannelBonding (Lane Deskew)(page 220)CHAN_BOND_SEQ_1_1_0CHAN_BOND_SEQ_1_1_1CHAN_BOND_SEQ_1_2_0CHAN_BOND_SEQ_1_2_1CHAN_BOND_SEQ_1_3_0CHAN_BOND_SEQ_1_3_1CHAN_BOND_SEQ_1_4_010-bitBinaryUsed in conjunction withCHAN_BOND_SEQ_1_ENABLE todefine channel bonding sequence 1.Configurable ChannelBonding (Lane Deskew)(page 220)CHAN_BOND_SEQ_1_4_1CHAN_BOND_SEQ_1_ENABLE_0CHAN_BOND_SEQ_1_ENABLE_14-bitBinarySets which parts of channel bondingsequence 1 are don't cares.Configurable ChannelBonding (Lane Deskew)(page 220)CHAN_BOND_SEQ_2_1_0CHAN_BOND_SEQ_2_1_1CHAN_BOND_SEQ_2_2_0CHAN_BOND_SEQ_2_2_1CHAN_BOND_SEQ_2_3_0CHAN_BOND_SEQ_2_3_1CHAN_BOND_SEQ_2_4_010-bitBinaryUsed in conjunction withCHAN_BOND_SEQ_2_ENABLE todefine the second channel bondingsequence.Configurable ChannelBonding (Lane Deskew)(page 224)CHAN_BOND_SEQ_2_4_1CHAN_BOND_SEQ_2_ENABLE_0CHAN_BOND_SEQ_2_ENABLE_14-bitBinarySets which parts of channel bondingsequence 2 are don't cares.Configurable ChannelBonding (Lane Deskew)(page 224)CHAN_BOND_SEQ_2_USE_0CHAN_BOND_SEQ_2_USE_1BooleanDetermines if the second channelbonding sequence is to be used.Configurable ChannelBonding (Lane Deskew)(page 224)CHAN_BOND_SEQ_LEN_0CHAN_BOND_SEQ_LEN_1IntegerDefines the length in bytes of thechannel bonding sequence that thetransceiver matches to detectopportunities for channel bonding.Configurable ChannelBonding (Lane Deskew)(page 224)CLK_COR_ADJ_LEN_0CLK_COR_ADJ_LEN_1IntegerDefines the size of the adjustment(number of bytes repeated or skipped)in a clock correction.Configurable ClockCorrection (page 213)CLK_COR_DET_LEN_0CLK_COR_DET_LEN_1IntegerDefines the length of the sequence thatthe transceiver matches to detectopportunities for clock correction.Configurable ClockCorrection (page 213)CLK_COR_INSERT_IDLE_FLAG_0CLK_COR_INSERT_IDLE_FLAG_1BooleanControls whether RXRUNDISP inputstatus indicates running disparity orinserted-idle (clock correctionsequence) flag.Configurable ClockCorrection (page 213)RocketIO GTX Transceiver User Guide www.xilinx.com 41UG198 (v3.0) October 30, 2009
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Appendix A: MGT to GTX Transceiver
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Infiniband 245PCI Express 245SATA 2
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TX PISO 149TX polarity control 147T
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