Xilinx UG198 Virtex-5 FPGA RocketIO GTX Transceiver, User Guide

Ports and AttributesTable 1-3:GTX_DUAL Port Summary (Cont’d)Port Dir Domain Description Section (Page)TXPOWERDOWN0[1:0]TXPOWERDOWN1[1:0]TXPREEMPHASIS0[3:0]TXPREEMPHASIS1[3:0]In TXUSRCLK2 (1) Powers down the TX lanes.In Async Controls the pre-emphasis.Power Control (page 111),Receive Detect Support forPCI Express Operation(page 154), TX Out-of-Band/Beacon Signaling(page 157)Configurable TX Driver(page 151)TXRESET0TXRESET1InAsyncResets the PCS of the GTXtransmitter, including the phaseadjust FIFO, the 8B/10B encoder,and the FPGA TX interface.Reset (page 102), FPGA TXInterface (page 122)TXRUNDISP0[3:0]TXRUNDISP1[3:0]OutTXUSRCLK2Indicates the current runningdisparity of the 8B/10B encoder.Configurable 8B/10BEncoder (page 131)TXSEQUENCE0[6:0]TXSEQUENCE1[6:0]InTXUSRCLK2Input to the TX Gearbox from asequence counter implementedin the FPGA logic.TX Gearbox (page 134)TXSTARTSEQ0TXSTARTSEQ1InTXUSRCLK2Input to the TX Gearbox from theFPGA logic indicating the start ofa TX sequence.TX Gearbox (page 134)TXUSRCLK0TXUSRCLK1InN/AProvides a clock for the internalTX PCS datapath.FPGA TX Interface(page 122), TX Buffering,Phase Alignment, and TXSkew Reduction (page 143)TXUSRCLK20TXUSRCLK21InN/ASynchronizes the FPGA logicwith the TX interface.FPGA TX Interface(page 122)Notes:1. TXPOWERDOWN0[1:0] and TXPOWERDOWN1[1:0] of the GTX_DUAL tile belong to the TXUSRCLK2 clock domain. This isdifferent from the GTP_DUAL tile implementation where TXPOWERDOWN0[1:0] and TXPOWERDOWN1[1:0] are asynchronous.Table 1-4 lists alphabetically the signal names, clock domains, directions, and descriptionsfor the CRC ports, and provides links to their detailed descriptions.Table 1-4:CRC Port SummaryPort Dir Domain Description Section (Page)CRCCLK In N/A CRC clock.Cyclic Redundancy Check(page 242)CRCDATAVALID In CRCCLKCRCDATAVALIDA In CRCCLKCRCDATAWIDTH[2:0] In CRCCLKIndicates valid data on 32-bitCRCIN inputs.Indicates valid data on 64-bitCRCIN inputs.Indicates how many input databytes are valid.Cyclic Redundancy Check(page 243)Cyclic Redundancy Check(page 242)Cyclic Redundancy Check(page 242)RocketIO GTX Transceiver User Guide www.xilinx.com 39UG198 (v3.0) October 30, 2009