High-Performance SAB 80C517A/83C517A-5 8-Bit CMOS Single ...

SAB 80C517A/83C517A-5Control of XRAM in the SAB 80C517AThere are two control bits in register SYSCON which control the use and the bus operationduring accesses to the additional On-Chip RAM (XRAM).Special Function Register SYSCONAddr. 0B1 H — — — — — — XMAP1 XMAP0 SYSCONBitXMAP0XMAP1FunctionGlobal enable/disable bit for XRAM memory.XMAP0 = 0: The access to XRAM (= On-Chip XDATA memory) is enabled.XMAP0 = 1: The access to XRAM is disabled. All MOVX accesses are performedby the external bus (reset state).Control bit for RD/WR signals during accesses to XRAM; this bit has noeffect if XRAM is disabled (XMAP0 = 1) or if addresses exceeding theXRAM address range are used for MOVX accesses.XMAP1 = 0: The signals RD and WR are not activated during accessesto XRAM.XMAP1 = 1: The signals RD and WR are activated during accesses toXRAM.Reset value of SYSCON is xxxx xx01B.The control bit XMAP0 is a global enable/disable bit for the additional On-Chip RAM (XRAM).If this bit is set, the XRAM is disabled, all MOVX accesses use external memory via the externalbus. In this case the SAB 80C517A does not use the additional On-Chip RAM and is compatiblewith the types without XRAM.Semiconductor Group 22