High-Performance SAB 80C517A/83C517A-5 8-Bit CMOS Single ...

SAB 80C517A/83C517A-5Power Down ModeThe power down mode is entered by two consecutive instructions directly following each other.The first instruction has to set the flag PDE (power down enable) and must not set PDS (powerdown set). The following instruction has to set the start bit PDS. Bits PDE and PDS willautomatically be cleared after having been set.The instruction that sets bit PDS is the last instruction executed before going into power downmode. The only exit from power down mode is a hardware reset.The status of all output lines of the controller can be looked up in table 8.Hardware Controlled Power Down ModeThe pin HWPD controls this mode. If it is on logic high level (inactive) the part is running in thenormal operating modes. If pin HWPD gets active (low level) the part enters the HardwarePower Down Mode; this is independent of the state of pin PE/SWD.HWPD is sampled once per machine cycle. If it is found active, the device starts a completeinternal reset sequence. The watchdog timer is stopped and its status flag WDTS is clearedexactly the same effects as a hardware reset. In this phase the power consumption is not yetreduced. After completion of the internal reset both oscillators of the chip are disabled. At thesame time the port pins and several control lines enter a floating state as shown in table 8. Inthis state the power consumption is reduced to the power down current IPD. Also the supplyvoltage can be reduced. Table 8 also lists the voltages which may be applied at the pins duringHardware Power Down Mode without affecting the low power consumption.Termination of HWPD Mode:This power down state is maintained while pin HWPD is held active. If HWPD goes to high level(inactive state) an automatic start up procedure is performed:– First the pins leave their floating condition and enter their default reset state(as they had immediately before going to float state).– Both oscillators are enabled (only if OWE = high). The oscillator watchdog’s RCoscillator starts up very fast (typ. less than 2 microseconds).– Because the oscillator watchdog is active it detects a failure condition if theon-chip oscillator hasn’t yet started. Hence, the watchdog keeps the part in resetand supplies the internal clock from the RC oscillator.– Finally, when the on-chip oscillator has started, the oscillator watchdog releasesthe part from reset with oscillator watchdog status flag not set.When automatic start of the watchdog was enabled (PE/SWD connected to V CC ),the Watchdog Timer will start, too (with its default reload value for time-out period).– The Reset pin overrides the Hardware Power Down function, i.e. if reset gets activeduring Hardware Power Down it is terminated and the device performs the normalreset function. (Thus, pin Reset has to be inactive during Hardware Power Down Mode).Semiconductor Group 52