High-Performance SAB 80C517A/83C517A-5 8-Bit CMOS Single ...

SAB 80C517A/83C517A-5CompareIn compare mode, the 16-bit values stored in the dedicated compare registers are comparedto the contents of the timer 2 register or the compare timer register. If the count value in thetimer registers matches one of the stored value, an appropriate output signal is generated atthe corresponding pin(s) and an interrupt is requested. Three compare modes are provided:Mode 0: Upon a match the output signal changes from low to high.It returns to low level at timer overflow.Mode 1: The transition of the output signal can be determined by software.A timer overflow signal does not affect the compare-output.Mode 2: In compare mode 2 the concurrent compare output pins on Port 5 are usedas follows (see figure 9)– When a compare match occurs with register COMSET, a high levelappears at the pins of port 5 whose corresponding bits in the maskregister SETMSK (address 0A5 H ) are set.– When a compare match occurs in register COMCLR, a low levelappears at the pins of port 5 whose corresponding bits in the maskregister CLRMSK (address 0A6 H ) are set.Additionally the Port 5 pins used for compare mode 2 may also bedirectly written to by write instructions to SFR P5. Of course, the pinscan also be read under program control.Compare registers CM0 to CM7 use additional compare latches when operated in mode 0.Figure 8 shows the function of these latches. The latches are implemented to prevent from lossof compare matches which may occur when loading of the compare values is not correlatedwith the timer count. The compare latches are automatically loaded from the compare registersat every timer overflow.CaptureThis feature permits saving of the actual timer/counter contents into a selected register uponan external event or a software write operation. Two modes are provided to 'freeze' the current16-bit value of timer 2 registers into a dedicated capture register.Mode 0: Capture is performed in response to a transition at the correspondingport 1 pins CC0 to CC3.Mode 1: Write operation into the low-order byte of the dedicated capture registercauses the timer 2 contents to be latched into this register.Semiconductor Group 38