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High-Performance SAB 80C517A/83C517A-5 8-Bit CMOS Single ...

High-Performance SAB 80C517A/83C517A-5 8-Bit CMOS Single ...

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<strong>SAB</strong> <strong>80C517A</strong>/<strong>83C517A</strong>-5Watchdog UnitsThe <strong>SAB</strong> <strong>80C517A</strong> offers two enhanced fail safe mechanisms, which allow an automaticrecovery from hardware failure or software upset:– programmable watchdog timer (WDT), variable from 512 µs up to appr. 1.1 s time-outperiod @12 MHz. Upward compatible to <strong>SAB</strong> 80515 watchdog.– oscillator watchdog (OWD), monitors the on-chip oscillator and forces the microcontrollerinto reset state, in case the on-chip oscillator fails, controls the restart fromthe Hardware Power Down Mode and provides clock for a fast internal reset after power-on.Programmable Watchdog TimerThe WDT can be activated by hardware or software.Hardware initialization is done when pin PE/SWD (Pin 4) is held high during RESET. The<strong>SAB</strong> <strong>80C517A</strong> then starts program execution with the WDT running. Since Pin PE/SWD isonly sampled during Reset (and hardware power down at parts with stepping code AD andlater) dynamical switching of the WDT is not possible.Software initialization is done by setting bit SWDT.A refresh of the watchdog timer is done by setting bits WDT and SWDT consecutively.A block diagram of the watchdog timer is shown in figure 11.When a watchdog timer resest occurs, the watchdog timer keeps on running, but a status flagWDTS is set. This flag can also be cleared by software.Figure 11Block Diagram of the Programmable Watchdog TimerSemiconductor Group 58

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