Ultra-Low-Power Digital Circuit Design - Microelectronic Systems ...

CHAPTER 2.SUBTHRESHOLD SOURCE-COUPLED LOGICto satisfy V SW = ∆V in > 4 · n · U T (n is the subthreshold slope factor and U T the thermalvoltage) in order to completely switch the current. In a technology with n = 1.5, thevoltage swing has to be at least 150 mV.For more complex gates, a systematic approach is needed to identify all the logic functionsthat can be implemented with a given number of logic stages. A binary decisiondiagram can be used to systematically generate all possible gate topologies for a givennumber of inputs [5].2.2.3 PMOS Load DevicesSTSCL gates require a pair of load `resistors' with a high resistivity that can be preciselycontrolled and that is relatively insensitive to process variations. This can be achieved byusing a pair of PMOS transistors biased by a gate voltage V P , and with their bulk terminal(the n-well tap) tied to the drain. The resulting load device has been shown to have areasonably linear resistivity and low sensitivity to process variations [3].2.2.4 Replica Bias CircuitIn order to maintain the desired circuit performance in the presence of PVT (process -voltage - temperature) variations, a feedback loop containing a replica circuit is used toset the gate voltage of the PMOS load devices. This replica circuit consists of a tailtransistor with a bulk-drain connected load transistor, both using the same dimensionsas their counterparts inside the logic gates. The output voltage of this replica stage isequal to V DD − I SS R L , the low voltage in a dierential output pair. The desired valueof V SW = I SS R L is fed as an input to a negative-feedback loop which controls the gatevoltage V P of the load device and therefore its resistance R L .2.3 Use of STSCL for cryptographic hardwareFigure 4.4 shows the power supply current waveform for the STSCL implementation ofthe ECC core presented in Chapter 3. Contrary to CMOS, STSCL exhibits a very atpower prole, with supply current uctuations of less than 5%. The (partially) symmetricnature of STSCL gates means that the transient current waveform is also much less datadependent.This reduces the risk of exposing secrets (e.g. the private key) to a side-channelattacker.2.4 Performance analysis2.4.1 Gate DelaysThe bulk-drain connected load device acts like a resistor with a large-signal resistanceR = V SWnode.I SSand together with the load capacitance C L creates an RC network at the outputThe dierential output of an STSCL gate switches with a time constant given by:10