Ultra-Low-Power Digital Circuit Design - Microelectronic Systems ...

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CHAPTER 3.ELLIPTIC CURVE CRYPTOGRAPHIC PROCESSORFigure 3.1: Basic architecture of the ECC coreThe processor's register le consists of six registers with 163 bits each, named with theletters A through F. Each register has an enable signal which has to be asserted by thestate machine if a dierent value is to be loaded into the register. A global reset signal(one of the inputs to the processor) can be used to initially set all registers to zero. Aglobal clock signal clocks the ip-ops in the register le and in the counter.To start a new operation, the system is reset and then the start signal is asserted. Thestart signal causes the FSM to leave the default state and progress through a number ofstates, rst loading the input data, then calculating the sum of the two input points, andthen the double of one of them.The rst two registers are equipped with multiplexers that are controlled from the FSM.Register A has the most diverse functionality. It can load the output of the ALU, thedata_in input, the output of register B, or one of three predened values.Register B can take either the output of register A or a left-shifted copy of its own value.This allows cyclic shifting of values in register B, used for feeding the operand to the ALUin a bit-serial fashion.The remaining registers C to F serve to store intermediate results. They each take theoutput of the previous register.3.4.1 ALUThe nite eld multiplier is implemented as a bit-serial unit. One of the operands is storedin register B and its MSB is an input to the ALU. During multiplication, register B isleft-shifted at each clock cycle; thus the operand is entered into the ALU bit-serially.The value of the current bit position of B is multiplied with the other operand (registerC) by an array of 163 AND gates. In each cycle, this partial product is added to therunning sum (register A) using an array of 162 XOR gates. If the result has a `1' at the20
CHAPTER 3.ELLIPTIC CURVE CRYPTOGRAPHIC PROCESSORbit-position m (the degree of the sum is equal to the degree of the reduction polynomial),the bits at positions corresponding to the reduction polynomial are ipped, again usingXOR gates. This step corresponds to the modulo operation which guarantees that thedegree of the running sum is less than m after each clock cycle.3.4.2 Finite State MachineThe Finite State Machine that is part of this hardware ECC implementation loads thecoordinates of the two points P 1 and P 2 into registers and then cycles through a numberof states in order to compute the sum P 1 + P 2 and the value 2 · P 1 . The result is thenoutput in projective coordinates at the ports x1_out, x2_out and z_out and the readysignal is asserted to signal completion of the calculations. The entire operation requiresroughly 1800 clock cycles.3.4.3 RegistersThe ECC core uses a register le with six 163-bit registers called regA, regB, ... regFto store intermediate results. Registers regA and regB have an input multiplexer whichselects the value to store according to the select bits generated in the FSM. The otherregisters form a circular shift memory where each register takes the output of the previousregister as its input.3.5 Standard CMOS implementationThe ECC core was implemented in the UMC 90nm logic/mixed-mode CMOS process usingthe Faraday standard cell library. The RTL code was synthesized using Synopsys <strong>Design</strong>Compiler and then placed and routed using Cadence Encounter. Synthesis constraintswere chosen to favor low power consumption over high performance. No special poweroptimization techniques were used and the library was not re-characterized for lower supplyvoltages. Therefore, power consumption measurements can be expected to give pessimisticresults.3.6 STSCL implementation3.6.1 Modications of the design ow and libraryThe STSCL implementation used the existing library described in [4] with some smallmodications.An analysis of the routing process with the existing library showed that the design wasdicult to route because of the many D ip-ops in the design. The existing layout ofthese ip-ops had been assembled from two copies of the existing layout for the 2-inputmultiplexer. This lead to a bad cell layout with a long wire in the metal 3 layer, creatingobstructions during the routing process. The D Flip-Flop layout was thus optimized toeliminate most of the routing in metal 3.21
Page 4 and 5: Contents1 Introduction 61.1 Low-pow
Page 7 and 8: CHAPTER 1.INTRODUCTIONI DS ≈ I 0
Page 9 and 10: CHAPTER 2.SUBTHRESHOLD SOURCE-COUPL
Page 17 and 18: 3 Elliptic curve cryptographic proc
Page 19: CHAPTER 3.ELLIPTIC CURVE CRYPTOGRAP
Page 23 and 24: 4 Results4.1 Design and simulation
Page 25 and 26: CHAPTER 4.RESULTS`wasting' current
Page 27 and 28: CHAPTER 4.RESULTS32.521.5Iss [mA]10
Page 29 and 30: 5 Outlook5.1 Possible improvements
Page 31: 6 ConclusionThis work successfully
Page 34 and 35: AppendixVHDL code for the nite eld
Page 36 and 37: 16 process ( c l k )17 begin18 i f
Page 38 and 39: 4 use IEEE .STD_LOGIC_UNSIGNED.ALL;
Page 40: 7172 v = axis ( ) ;7374 text ( v (

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