Ultra-Low-Power Digital Circuit Design - Microelectronic Systems ...

2 Subthreshold Source-Coupled Logic2.1 OverviewSource-coupled logic, also known under the more general term current-mode logic (CML)is a group of logic families that use transistor dierential pairs to switch a constant biascurrent towards one of two branches representing the two terminals of a dierential outputsignal. In a MOS implementation, an NMOS tail transistor biased with a constant gatevoltage acts as a current source that draws a constant current I ss from the supply. Logicoperation takes place by steering the tail current to one of the two load devices. This canbe achieved by a network of dierential pairs controlled by the (dierential) gate inputvoltages.The output signal is created by two load `resistors' that convert the dierence in currentin their respective branches into a dierential output voltage. The value of these resistorsis chosen such that I ss creates a voltage drop of V SW = I SS R L when the tail currentpasses through them. One of the output terminals will therefore be at a voltage of V L =V DD − V SW , the other at V H = V DD .Subthreshold source-coupled logic (STSCL, [1, 2, 3]) is a variant of current-mode logic inwhich all transistors are operating in the subthreshold region. Since in STSCL, operationis based on switching a subthreshold current between the two branches of the logic gate,the problem of leakage power consumption is virtually nonexistent 1 .2.2 Description of STSCL CircuitsFigure 2.1 shows the STSCL logic style proposed in [3]. It uses a replica bias circuitwhich allows the tail current to be adjusted over a wide range, enabling circuits that candynamically adapt to available power and required speed. Operation of the circuits isindierent to variations in supply voltage, as long as the replica bias circuit is able togenerate a large enough bias voltage for the desired tail current. As shown in Figure 2.2,supply voltages as low as 0.3 V are possible for a tail current of 100 pA. Gates with higherdriving strength require a slightly higher V DD if device sizes are kept the same, becausethe gate-to-source voltage of the active dierential pair transistor is higher.One particularity with current-mode logic styles is the fact that they draw a constantcurrent, even when no switching takes place. For good energy-per-operation eciency, itis therefore important to design circuits with a high activity rate.1 As long as the currents in the p-n junction formed by the source and bulk of the PMOS load devices aresmall compared to the bias current.8