Ultra-Low-Power Digital Circuit Design - Microelectronic Systems ...

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4 use IEEE .STD_LOGIC_UNSIGNED.ALL;567 entity xor_2 i s8 Port ( a : in s t d _ l o g i c ;9 b : in s t d _ l o g i c ;10 c : out s t d _ l o g i c ) ;11 end xor_2 ;1213 architecture B e h a v i o r a l of xor_2 i s1415 begin1617 c
15 x p o i n t s = AF1 . data ( : , 1 ) ;16 vout1 = AF1 . data ( : , 2 : 2 : Nsamples ∗2) ;17 vin2 = AF2 . data ( : , 1 ) ;18 vout2 = AF2 . data ( : , 2 : 2 : Nsamples ∗2) ;1920 F1 = vout1 ;2122 F2 = [ ] ;23 for i = 1 : Nsamples24 F2 = [ F2 interp1 ( vout2 ( : , i ) , vin2 , x p o i n t s ) ] ;25 end2627 plot ( xpoints , F1 )28 hold on29 plot ( xpoints , F2 )30 %a x i s ( [ 0 , Vdd , 0 , Vdd ] ) ;31 axis e q u a l ;3233 % r o t a t e d system o f c o o r d i n a t e s34 v1 = ( x p o i n t s ∗ ones ( 1 , Nsamples ) + vout1 ) / sqrt ( 2 ) ;35 u1 = ( x p o i n t s ∗ ones ( 1 , Nsamples ) − vout1 ) / sqrt ( 2 ) ;36 v2 = ( x p o i n t s ∗ ones ( 1 , Nsamples ) + vout2 ) / sqrt ( 2 ) ;37 u2 = −( x p o i n t s ∗ ones ( 1 , Nsamples ) − vout2 ) / sqrt ( 2 ) ;3839 % p o i n t s on the new ' x'− a x i s40 % l e s s than vdd/ s q r t 2 to t r u n c a t e the e x t r a p o l a t e d ' t a i l s '41 u p o i n t s = linspace ( −0.9∗Vdd/ sqrt ( 2 ) , 0 . 9 ∗ Vdd/ sqrt ( 2 ) , i n t e r p ) ' ;4243 v1resamp = [ ] ;44 v2resamp = [ ] ;4546 % i n t e r p o l a t e the curve at the new p o i n t s47 for i = 1 : Nsamples48 v1resamp = [ v1resamp interp1 ( u1 ( : , i ) , v1 ( : , i ) , u p o i n t s ) ] ;49 v2resamp = [ v2resamp interp1 ( u2 ( : , i ) , v2 ( : , i ) , u p o i n t s ) ] ;50 end5152 %v1resamp ( isnan ( v1resamp ) ) = 0 ;53 %v2resamp ( isnan ( v2resamp ) ) = 0 ;5455 %p l o t ( upoints , v1resamp , upoints , v2resamp ) ;56 axis e q u a l ;5758 s nr = [ ] ;5960 for i = 1 : Nsamples61 d i f f = ( v1resamp ( : , i ) ∗ ones ( 1 , Nsamples )−v2resamp ) ;62 s nr = [ s n r ; min(max( d i f f ( 1 : round ( i n t e r p /2) , : ) , [ ] , 1) ,63 max(− d i f f (round ( i n t e r p /2) : i n t e r p , : ) , [ ] , 1) ) '/ sqrt( 2 ) ] ;64 end6566 figure ( )67 h i s t f i t ( snr , 2 0 ) ;6869 [mu, s i g ] = n o r m f i t ( snr )70 xlabel ( ' S t a t i c Noise Margin [V] ' ) ;39
Page 4 and 5: Contents1 Introduction 61.1 Low-pow
Page 7 and 8: CHAPTER 1.INTRODUCTIONI DS ≈ I 0
Page 9 and 10: CHAPTER 2.SUBTHRESHOLD SOURCE-COUPL
Page 17 and 18: 3 Elliptic curve cryptographic proc
Page 19 and 20: CHAPTER 3.ELLIPTIC CURVE CRYPTOGRAP
Page 21 and 22: CHAPTER 3.ELLIPTIC CURVE CRYPTOGRAP
Page 23 and 24: 4 Results4.1 Design and simulation
Page 25 and 26: CHAPTER 4.RESULTS`wasting' current
Page 27 and 28: CHAPTER 4.RESULTS32.521.5Iss [mA]10
Page 29 and 30: 5 Outlook5.1 Possible improvements
Page 31: 6 ConclusionThis work successfully
Page 34 and 35: AppendixVHDL code for the nite eld
Page 36 and 37: 16 process ( c l k )17 begin18 i f
Page 40: 7172 v = axis ( ) ;7374 text ( v (

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