Ultra-Low-Power Digital Circuit Design - Microelectronic Systems ...

8 entity x o r s h i f t i s9 generic ( n b i t s : n a t u r a l := 8) ;10 port ( s h i f t e d _ b i t : in s t d _ l o g i c ;11 m u l t i p l i c a n d : in s t d _ l o g i c _ v e c t o r ( n b i t s −1 downto 0) ;12 sum_in : in s t d _ l o g i c _ v e c t o r ( n b i t s −2 downto 0) ;13 sum_out : out s t d _ l o g i c _ v e c t o r ( n b i t s −1 downto 0)14 ) ;15 end x o r s h i f t ;161718 architecture arch of x o r s h i f t i s1920 component and_221 port (22 a : in s t d _ l o g i c ;23 b : in s t d _ l o g i c ;24 c : out s t d _ l o g i c25 ) ;26 end component and_2 ;2728 component xor_229 port (30 a : in s t d _ l o g i c ;31 b : in s t d _ l o g i c ;32 c : out s t d _ l o g i c33 ) ;34 end component xor_2 ;353637 signal and_temp : s t d _ l o g i c _ v e c t o r ( n b i t s −1 downto 0) ;3839 begin4041 and_gate : for i in 0 to n b i t s −1 generate42 Comp : and_2 port map (43 a => s h i f t e d _ b i t ,44 b => m u l t i p l i c a n d ( i ) ,45 c => and_temp ( i )46 ) ;47 end generate ;4849 xor_gate : for i in 1 to n b i t s −1 generate50 Comp : xor_2 port map (51 a => and_temp ( i ) ,52 b => sum_in ( i −1) ,53 c => sum_out ( i )54 ) ;55 end generate ;5657 sum_out ( 0 )