Ultra-Low-Power Digital Circuit Design - Microelectronic Systems ...

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CHAPTER 3.ELLIPTIC CURVE CRYPTOGRAPHIC PROCESSORFigure 3.2: Modied D Flip-Flop layout3.6.2 Library SpecicationsThe STSCL implementation of the ECC core uses the library with the characterizationparameters listed in Table 3.2.V DDV SWI SS,x11.2 V0.2 V1nATable 3.2: Library cornerIn order to nd the best conguration, the library was characterized for dierent valuesfor the bias current (200pA, 1nA, 5nA). It was found that the 1nA variant is the bestchoice for the present design, due to the fact that the range of available gates (drivingstrengths from x1 to x32) covers the requirements for synthesis. The nal P&R resultsshow that most of the gates have an intermediate driving strength, and only relatively fewx1 and x32 gates are present. This suggests that the chosen bias current is appropriate forthis design.22
4 Results4.1 <strong>Design</strong> and simulation owThe two implementations were synthesized, placed and routed as described in the previouschapter. The CMOS design was then imported in Cadence Virtuoso and a device andcapacitance extraction from the layout was performed. This extracted netlist was thensimulated using Cadence Spectre, with a VCD (Verilog value change dump) le providingthe input stimuli as well as the correct output values for verication.The STSCL design could not be simulated correctly using this approach. It was simulatedin Nanosim using the Verilog netlist and extracted capacitance le (SPEF) generatedin Cadence Encounter. A supply voltage of 1 V was used.Figure 4.1: Output waveform of one of the regB ip-ops with the corresponding clocksignalA comparison of output signals with the results from VHDL simulation shows that thedesign is operating correctly at a frequency of 100 kHz. Figure 4.1 shows an example of aclock and signal waveform.4.2 Performance comparisonTable 4.1 gives a summary of the results obtained for the implementations of the ECC coreusing the Faraday CMOS library as well as the STSCL library. Figure 4.2 shows the nallayouts for both implementations.It can be seen from Figure 4.2 that the area of the STSCL implementation is roughly8.5 times larger. This is mainly due to the large size of cells in the STSCL library. For23
Page 4 and 5: Contents1 Introduction 61.1 Low-pow
Page 7 and 8: CHAPTER 1.INTRODUCTIONI DS ≈ I 0
Page 9 and 10: CHAPTER 2.SUBTHRESHOLD SOURCE-COUPL
Page 17 and 18: 3 Elliptic curve cryptographic proc
Page 19 and 20: CHAPTER 3.ELLIPTIC CURVE CRYPTOGRAP
Page 21: CHAPTER 3.ELLIPTIC CURVE CRYPTOGRAP
Page 25 and 26: CHAPTER 4.RESULTS`wasting' current
Page 27 and 28: CHAPTER 4.RESULTS32.521.5Iss [mA]10
Page 29 and 30: 5 Outlook5.1 Possible improvements
Page 31: 6 ConclusionThis work successfully
Page 34 and 35: AppendixVHDL code for the nite eld
Page 36 and 37: 16 process ( c l k )17 begin18 i f
Page 38 and 39: 4 use IEEE .STD_LOGIC_UNSIGNED.ALL;
Page 40: 7172 v = axis ( ) ;7374 text ( v (

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