Tutorial for the Semi Custom Part of the Image Processing System
Tutorial for the Semi Custom Part of the Image Processing System
Tutorial for the Semi Custom Part of the Image Processing System
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36 set NBITS_PIXEL 837 set NBITS_HISTOGRAM 1838 set CLK_NAME clock39 # all time values are in ns40 set CLK_PERIOD 10;41 set INPUT_DELAY 2;42 set OUTPUT_DELAY 2;43 set OPERATING_COND WORST-IND4445 # -----------------------------------------------------------------------------46 # Flags that drive <strong>the</strong> script behavior ( can be changed )47 #48 # DB_FORMAT (db | ddc )49 # if db, use <strong>the</strong> old DB <strong>for</strong>mat to store design in<strong>for</strong>mation50 # if ddc, use <strong>the</strong> new XG <strong>for</strong>mat to store design in<strong>for</strong>mation ( recommended )51 # SHARE_RESOURCES (0 | 1)52 # if 1, <strong>for</strong>ce <strong>the</strong> tool to share resources as much as possible53 # if 0, no resource sharing54 # COMPILE_SIMPLE (0 | 1)55 # if 1, only do a single compile with default arguments56 # if 0, do a two-step compilation with ungrouping in between57 # OPT ( string )58 # can be used to generate different mapped file names59 # -----------------------------------------------------------------------------60 set DB_FORMAT ddc61 set SHARE_RESOURCES 162 set COMPILE_SIMPLE 163 set OPT " _clock10ns_share "64${ VHDL_ENTITY } _WIDTH$ { WIDTH } _HEIGHT$ { HEIGHT } _NBITS_PIXEL$ { NBITS_PIXEL } _NBITS_HISTOGRAM$ { NBI65 # -----------------------------------------------------------------------------66 # File names67 # -----------------------------------------------------------------------------68 set SOURCE_FILE_NAME ${ VHDL_ENTITY }69 set ROOT_FILE_NAME ↵70 set VHDL_SOURCE_FILE_NAME ${ SOURCE_FILE_NAME } .vhd71 set ELAB_FILE_NAME ${ ROOT_FILE_NAME }${ OPT } _elab72 set MAPPED_FILE_NAME ${ ROOT_FILE_NAME }${ OPT } _mapped73 set DB_ELAB_FILE_NAME ${ ELAB_FILE_NAME } .$DB_FORMAT74 set DB_MAPPED_FILE_NAME ${ MAPPED_FILE_NAME } .$DB_FORMAT75 set VHDL_NETLIST_FILE_NAME ${ MAPPED_FILE_NAME } .vhd76 set VLOG_NETLIST_FILE_NAME ${ MAPPED_FILE_NAME }.v77 set SDF_FILE_NAME ${ MAPPED_FILE_NAME } .sdf78 set SDC_FILE_NAME ${ MAPPED_FILE_NAME } .sdc79 set RPT_AREA_FILE_NAME ${ MAPPED_FILE_NAME } _area.rpt80 set RPT_TIMING_FILE_NAME ${ MAPPED_FILE_NAME } _timing.rpt81 set RPT_RESOURCES_FILE_NAME ${ MAPPED_FILE_NAME } _resources.rpt82 set RPT_REFERENCES_FILE_NAME ${ MAPPED_FILE_NAME } _references.rpt83 set RPT_CELLS_FILE_NAME ${ MAPPED_FILE_NAME } _cells.rpt8485 # -----------------------------------------------------------------------------86 # Absolute paths87 # -----------------------------------------------------------------------------88 set VHDL_SOURCE_FILE ${ PROJECT_DIR }/ HDL / RTL /${ VHDL_SOURCE_FILE_NAME }89 set VHDL_NETLIST_FILE ${ PROJECT_DIR }/ HDL / GATE /${ VHDL_NETLIST_FILE_NAME }90 set VLOG_NETLIST_FILE ${ PROJECT_DIR }/ HDL / GATE /${ VLOG_NETLIST_FILE_NAME }91 set DB_ELAB_FILE ${ PROJECT_DIR }/ SYN /DB/${ DB_ELAB_FILE_NAME }92 set DB_MAPPED_FILE ${ PROJECT_DIR }/ SYN /DB/${ DB_MAPPED_FILE_NAME }93 set SDF_FILE ${ PROJECT_DIR }/ SYN / TIM /${ SDF_FILE_NAME }94 set SDC_FILE ${ PROJECT_DIR }/ SYN / SDC /${ SDC_FILE_NAME }95 set RPT_AREA_FILE ${ PROJECT_DIR }/ SYN / RPT /${ RPT_AREA_FILE_NAME }96 set RPT_TIMING_FILE ${ PROJECT_DIR }/ SYN / RPT /${ RPT_TIMING_FILE_NAME }vlsi2semicustomtutorial.tex Rev: 3, March 27, 2007 13
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