Tutorial for the Semi Custom Part of the Image Processing System

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Table 2: Interface of the histogram calculation blockName Type Default Description(a) GenericsWIDTH positive 320 Width of frameHEIGHT positive 240 Height of frameNBITS_PIXEL positive 8 Bits per pixelNBITS_HISTOGRAM positive 18 Bits for each histogram entry(b) PortsName Class Dir. Type Descriptionclock signal in std_logic Clockreset signal in std_logic Reset (active low)frame_start signal in std_logic Frame startvideo_clock signal in std_logic Video clockvideo_in signal in std_logic_vector(NBITS_PIXEL - 1 downto 0) Digitised video signaldone signal out std_logic Histogram doneread_request signal in std_logic Read request forthe histogram dataaddress signal in std_logic_vector(NBITS_PIXEL - 1 downto 0) Address to readfromdata_out signal out std_logic_vector(NBITS_HISTOGRAM - 1 downto 0) Output for histogramdataram_rw_select signal out std_logic Read or write modeselect for RAMram_enable signal out std_logic Enable signal forRAMram_address signal out std_logic_vector(NBITS_PIXEL - 1 downto 0) Address for RAMram_data_in signal in std_logic_vector(NBITS_HISTOGRAM - 1 downto 0) Data read fromRAMram_data_out signal out std_logic_vector(NBITS_HISTOGRAM - 1 downto 0) Data written toRAMram_reset signal out std_logic Reset for RAM (activelow)4 Rev: 3, March 27, 2007 vlsi2_semi_custom_tutorial.tex
eset = 0START PIXELframe start = 1 ∧ video clock = 1READ HISTOGRAMpixel count ≥ WIDTH · HEIGHTWAIT RAMvideo clock = 1WRITE HISTOGRAMpixel count < WIDTH · HEIGHTREAD PIXELStateSTART_PIXELREAD_PIXELREAD_HISTOGRAMWAIT_RAMWRITE_HISTOGRAMDescriptionWait for first frame pixel, read its value, and answer requests for histogram entriesWait for next pixel and read its valueRead the histogram entry corresponding to current pixelWait for RAM to complete the read requestWrite back the incremented histogram entry corresponding to the current pixelFigure 1: State diagram of the histogram calculation blockThe single port RAM is private to the synthesisable histogram calculation block, which also governsexternal accesses to the RAM. Therefore, both blocks will be encapsulated into a histogram topblock (Listing 3).The second task is to create the testbench for the histogram top block. The testing approach is similarto the one used for the single port RAM (Listing 2). The testbench shall feed the histogram block afterthe reset with a random video signal, from which it calculates in parallel the histogram. After the blocksignals that it finished the calculation of the histogram for the current frame, the histogram shall be readout and compared with the histogram calculated by the testbench. If there are discrepancies, an errormessage shall be generated by the simulator.3.2. Session 2: Synthesis of the Gate-Level Netlist of the Histogram BlockThe Synthesis of the gate-level netlist from the VHDL RTL model of the histogram block will be doneaccording to the description in Vachoux [5], Chapter 3 using Synopsys Design Vision. A Tcl scriptSYN/BIN/histogram_syn.tcl (Listing 4, downloadable from the Moodle site) can be used to automatisethe synthesis for different constraints. To run the Tcl script, execute the following command in a Unix shellfrom the IPS/ project directory:vlsi2_semi_custom_tutorial.tex Rev: 3, March 27, 2007 5
Page 1 and 2: EPFL/STI/IMM/LSMBâtiment ELD, Stat
Page 3: Table 1: Interface of the Random Ac
Page 7 and 8: 18 -- specified address at each pos
Page 9 and 10: 50 -- component generics51 constant
Page 11 and 12: 2425 library ieee ;26 use ieee . st
Page 13 and 14: 36 set NBITS_PIXEL 837 set NBITS_HI
Page 15 and 16: 158 compile159 } else { compile -ma
Page 17 and 18: 69 Pin: ram_data_in [16] n70 Pin: r
Page 19 and 20: 86 # if 1, create a clock tree spec
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Tutorial for the Semi Custom Part of the Image Processing System

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