Tutorial for the Semi Custom Part of the Image Processing System

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24 # Date Version Author Description25 # 2007 -03-25 1.0 maehne Created on the base of addsub_par.tcl ( vachoux )26 # -----------------------------------------------------------------------------272829 set PROJECT_DIR [ pwd ]3031 # -----------------------------------------------------------------------------32 # Design related information ( can be changed )33 # -----------------------------------------------------------------------------34 set DESIGN histogram_WIDTH320_HEIGHT240_NBITS_PIXEL8_NBITS_HISTOGRAM183536 set TIM_LIBRARY C35_CORELIB37 set TIM_OC_MAX WORST-IND ;# TYPICAL | WORST | WORST-IND38 set TIM_OC_MIN BEST-IND ;# TYPICAL | BEST | BEST-IND3940 # Floorplan settings41 #42 set FP_ASPECT_RATIO 1.043 set FP_ROW_DENSITY 0 .85 ;# percent44 set FP_CORE2IO 16 ;# micron4546 # Power ring and settings47 #48 set PR_WIDTH 4 ;# micron49 set PR_SPACING 0.6 ;# micron50 set PR_LAYER_TB MET1 ;# top and bottom layer51 set PR_LAYER_LR MET2 ;# left and right layer5253 # Power stripe settings54 #55 set ST_NUM_SETS 1 ;# number of sets56 set ST_SPACING 1 ;# micron57 set ST_LAYER_V $PR_LAYER_LR58 set ST_WIDTH 2 ;# micron59 set ST_XOFS_R 100 ;# micron60 set ST_XOFS_L 100 ;# micron6162 # Placement settings63 #64 set PL_EFFORT -high ;# -low | -medium | -high6566 # Clock tree synthesis settings67 #68 set CTS_BUFFER BUF269 set CTS_INV INV07071 # Filler cells72 #73 set FILLER_CELLS \74 " FILLRT25 ␣ FILLRT10 ␣ FILLRT5 ␣ FILLRT2 ␣ FILLRT1 ␣ FILL25 ␣ FILL10 ␣ FILL5 ␣ FILL2 ␣ FILL1 "7576 # -----------------------------------------------------------------------------77 # Flags that drive the script behavior ( can be changed )78 #79 # ADD_STRIPES (0 | 1)80 # if 1, add stripes81 # PLACE_TIMING (0 | 1)82 # if 1, do a timing driven placement83 # CLOCK_TREE (0 | 1)84 # if 1, create a clock tree85 # CTS_CREATE_SPEC (0 | 1)18 Rev: 3, March 27, 2007 vlsi2semicustomtutorial.tex
86 # if 1, create a clock tree specification file with default values87 # ROUTE_TIMING (0 | 1)88 # if 1, do a timing driven routing89 # OPT ( string )90 # can be used to have different generated file names91 # -----------------------------------------------------------------------------92 set ADD_STRIPES 193 set PLACE_TIMING 194 set CLOCK_TREE 195 set CTS_CREATE_SPEC 096 set ROUTE_TIMING 197 set OPT " _clock10ns_cts "9899 # -----------------------------------------------------------------------------100 # File names101 # -----------------------------------------------------------------------------102 set CONF_FILE_NAME ${ DESIGN } .conf103 set IO_FILE_NAME ${ DESIGN } .io104 set DESIGN_NAME ${ DESIGN }${ OPT }105 set SAVE_DESIGN_FP_NAME ${ DESIGN_NAME } -fplan.enc106 set SAVE_DESIGN_PR_NAME ${ DESIGN_NAME } -pring.enc107 set SAVE_DESIGN_PL_NAME ${ DESIGN_NAME } -placed.enc108 set SAVE_DESIGN_PF_NAME ${ DESIGN_NAME } -placed_filled.enc109 set SAVE_DESIGN_CT_NAME ${ DESIGN_NAME } -cts.enc110 set SAVE_DESIGN_RO_NAME ${ DESIGN_NAME } -routed.enc111 set TIM_RCDB_NAME ${ DESIGN_NAME } .rcdb112 set SDF_FILE_NAME ${ DESIGN_NAME } -routed.sdf113 set SPEF_FILE_NAME ${ DESIGN_NAME } -routed.spef114 set RPT_CHECK_TA_NAME ${ DESIGN_NAME } -checkta.rpt115 set RPT_REPORT_TA_NAME ${ DESIGN_NAME } -ta.rpt116 set RPT_SLACK_NAME ${ DESIGN_NAME } -slack.rpt117 set RPT_GATE_COUNT_NAME ${ DESIGN_NAME } -gate_count.rpt118 set RPT_NOTCH_NAME ${ DESIGN_NAME } -notch.rpt119 set RPT_CONN_NAME ${ DESIGN_NAME } -conn.rpt120 set RPT_GEOM_NAME ${ DESIGN_NAME } -geom.rpt121 set RPT_DENSITY_NAME ${ DESIGN_NAME } -density.rpt122 set VLOG_NETLIST_SIM_NAME ${ DESIGN_NAME } -routed.v123 set VLOG_NETLIST_LVS_NAME ${ DESIGN_NAME } -routed_lvs.v124 set CTS_SPEC_NAME ${ DESIGN_NAME } -spec.cts125 set CTS_RGUIDE_NAME ${ DESIGN_NAME } -guide.cts126 set CTS_RPT_NAME ${ DESIGN_NAME } -cts.rpt127 set GDS_FILE_NAME ${ DESIGN_NAME } .gds128129 # -----------------------------------------------------------------------------130 # Absolute paths131 # -----------------------------------------------------------------------------132 set CONF_FILE ${ PROJECT_DIR }/ PAR / CONF /${ CONF_FILE_NAME }133 set IO_FILE ${ PROJECT_DIR }/ PAR / CONF /${ IO_FILE_NAME }134 set SAVE_DESIGN_FP_FILE ${ PROJECT_DIR }/ PAR /DB/${ SAVE_DESIGN_FP_NAME }135 set SAVE_DESIGN_PR_FILE ${ PROJECT_DIR }/ PAR /DB/${ SAVE_DESIGN_PR_NAME }136 set SAVE_DESIGN_PL_FILE ${ PROJECT_DIR }/ PAR /DB/${ SAVE_DESIGN_PL_NAME }137 set SAVE_DESIGN_PF_FILE ${ PROJECT_DIR }/ PAR /DB/${ SAVE_DESIGN_PF_NAME }138 set SAVE_DESIGN_CT_FILE ${ PROJECT_DIR }/ PAR /DB/${ SAVE_DESIGN_CT_NAME }139 set SAVE_DESIGN_RO_FILE ${ PROJECT_DIR }/ PAR /DB/${ SAVE_DESIGN_RO_NAME }140 set SDF_FILE ${ PROJECT_DIR }/ PAR / TIM /${ SDF_FILE_NAME }141 set SPEF_FILE ${ PROJECT_DIR }/ PAR / TIM /${ SPEF_FILE_NAME }142 set TIM_RCDB_FILE ${ PROJECT_DIR }/ PAR / TIM /${ TIM_RCDB_NAME }143 set RPT_CHECK_TA_FILE ${ PROJECT_DIR }/ PAR / RPT /${ RPT_CHECK_TA_NAME }144 set RPT_REPORT_TA_FILE ${ PROJECT_DIR }/ PAR / RPT /${ RPT_REPORT_TA_NAME }145 set RPT_SLACK_FILE ${ PROJECT_DIR }/ PAR / RPT /${ RPT_SLACK_NAME }146 set RPT_GATE_COUNT_FILE ${ PROJECT_DIR }/ PAR / RPT /${ RPT_GATE_COUNT_NAME }147 set RPT_NOTCH_FILE ${ PROJECT_DIR }/ PAR / RPT /${ RPT_NOTCH_NAME }vlsi2semicustomtutorial.tex Rev: 3, March 27, 2007 19
Page 1 and 2: EPFL/STI/IMM/LSMBâtiment ELD, Stat
Page 3 and 4: Table 1: Interface of the Random Ac
Page 5 and 6: eset = 0START PIXELframe start = 1
Page 7 and 8: 18 -- specified address at each pos
Page 9 and 10: 50 -- component generics51 constant
Page 11 and 12: 2425 library ieee ;26 use ieee . st
Page 13 and 14: 36 set NBITS_PIXEL 837 set NBITS_HI
Page 15 and 16: 158 compile159 } else { compile -ma
Page 17: 69 Pin: ram_data_in [16] n70 Pin: r
Page 21 and 22: 210211 # --------------------------
Page 23 and 24: 334 # -----------------------------

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