Tutorial for the Semi Custom Part of the Image Processing System

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97 set RPT_RESOURCES_FILE ${ PROJECT_DIR }/ SYN / RPT /${ RPT_RESOURCES_FILE_NAME }98 set RPT_REFERENCES_FILE ${ PROJECT_DIR }/ SYN / RPT /${ RPT_REFERENCES_FILE_NAME }99 set RPT_CELLS_FILE ${ PROJECT_DIR }/ SYN / RPT /${ RPT_CELLS_FILE_NAME }100101 # -----------------------------------------------------------------------------102 # Analyze RTL source103 # -----------------------------------------------------------------------------104 analyze -format vhdl -lib WORK $VHDL_SOURCE_FILE105106 # -----------------------------------------------------------------------------107 # Elaborate design108 # -----------------------------------------------------------------------------109 elaborate $VHDL_ENTITY \110 -arch $VHDL_ARCH \111 -lib DEFAULT -update \112 -param " WIDTH=$ { WIDTH },␣ HEIGHT=$ { HEIGHT },␣ NBITS_PIXEL=$ { NBITS_PIXEL },␣↵NBITS_HISTOGRAM=$ { NBITS_HISTOGRAM }"113114 check_design115116 # -----------------------------------------------------------------------------117 # Define environment118 # -----------------------------------------------------------------------------119 set_operating_conditions -library c35_CORELIB $OPERATING_COND120121 # -----------------------------------------------------------------------------122 # Define constraints123 # -----------------------------------------------------------------------------124 create_clock -name $CLK_NAME -period $CLK_PERIOD [ get_ports $CLK_NAME ]125126 set_input_delay $INPUT_DELAY -clock $CLK_NAME [ list [ all_inputs ]]127 set_output_delay $OUTPUT_DELAY -clock $CLK_NAME [ list [ all_outputs ]]128129 set_max_area 0130131 # Use only plain DFF cells132 set_dont_use [ list c35_CORELIB.db:c35_CORELIB / DFE* \133 c35_CORELIB.db:c35_CORELIB / DFS* \134 c35_CORELIB.db:c35_CORELIB / TF* \135 c35_CORELIB.db:c35_CORELIB / JK* ]136137 set_fix_multiple_port_nets -all138139 # -----------------------------------------------------------------------------140 # Set resource allocation and implementation141 # -----------------------------------------------------------------------------142 set_resource_implementation use_fastest143 if { $SHARE_RESOURCES } {144 set_resource_allocation area_only145 } else {146 set_resource_allocation none147 }148149 # -----------------------------------------------------------------------------150 # Save elaborated design and constraints151 # -----------------------------------------------------------------------------152 write -hierarchy -format $DB_FORMAT -output $DB_ELAB_FILE153154 # -----------------------------------------------------------------------------155 # Map design to gates156 # -----------------------------------------------------------------------------157 if { $COMPILE_SIMPLE } {14 Rev: 3, March 27, 2007vlsi2}semicustomtutorial.tex
158 compile159 } else { compile -map_effort medium -area_effort medium160 ungroup -all -flatten161 compile -incremental -map_effort high162 }163164 # -----------------------------------------------------------------------------165 # Save mapped design166 # -----------------------------------------------------------------------------167 write -hierarchy -format $DB_FORMAT -output $DB_MAPPED_FILE168169 # -----------------------------------------------------------------------------170 # Generate reports171 # -----------------------------------------------------------------------------172 report_area -nosplit > $RPT_AREA_FILE173 report_timing -path full \174 -delay max \175 -nworst 1 \176 -max_paths 1 \177 -significant_digits 2 \178 -nosplit \179 -sort_by group \180 > $RPT_TIMING_FILE181 report_resources -nosplit -hierarchy > $RPT_RESOURCES_FILE182 report_reference -nosplit > $RPT_REFERENCES_FILE183 report_cell -nosplit > $RPT_CELLS_FILE184185 # -----------------------------------------------------------------------------186 # Generate VHDL netlist187 # -----------------------------------------------------------------------------188 change_names -rule vhdl -hierarchy -verbose189 write -format vhdl -hierarchy -output $VHDL_NETLIST_FILE190191 # -----------------------------------------------------------------------------192 # Generate SDF data193 # -----------------------------------------------------------------------------194 write_sdf -version 2.1 $SDF_FILE195196 # -----------------------------------------------------------------------------197 # Generate Verilog netlist198 #199 # The design is reloaded from scratch to avoid potential naming problems200 # when using the netlist for placement and routing201 # -----------------------------------------------------------------------------202 remove_design -all203 read_file -format $DB_FORMAT $DB_MAPPED_FILE204 change_names -rule verilog -hierarchy -verbose205 write -format verilog -hierarchy -output $VLOG_NETLIST_FILE206207 # -----------------------------------------------------------------------------208 # Save system constraints209 # -----------------------------------------------------------------------------210 write_sdc -nosplit $SDC_FILEListing 5: Cadence First Encounter IO assignment file for the histogram calculation block1 # #####################################################2 # #3 # Cadence Design Systems, Inc. #4 # Cadence (R) Encounter (TM) IO Assignments #5 # #6 # #####################################################vlsi2semicustomtutorial.tex Rev: 3, March 27, 2007 15
Page 1 and 2: EPFL/STI/IMM/LSMBâtiment ELD, Stat
Page 3 and 4: Table 1: Interface of the Random Ac
Page 5 and 6: eset = 0START PIXELframe start = 1
Page 7 and 8: 18 -- specified address at each pos
Page 9 and 10: 50 -- component generics51 constant
Page 11 and 12: 2425 library ieee ;26 use ieee . st
Page 13: 36 set NBITS_PIXEL 837 set NBITS_HI
Page 17 and 18: 69 Pin: ram_data_in [16] n70 Pin: r
Page 19 and 20: 86 # if 1, create a clock tree spec
Page 21 and 22: 210211 # --------------------------
Page 23 and 24: 334 # -----------------------------

Tutorial for the Semi Custom Part of the Image Processing System

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