Tutorial for the Semi Custom Part of the Image Processing System

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[11]edatp1@immsunsrv2-IPS> dc_shell -f SYN/BIN/histogram_syn.tclThe Tcl script can serve as a template for synthesis scripts for other digital blocks. An introduction forthe usage of Tcl in the context of (Synopsys) EDA tools is given in Syn [4].The post-synthesis simulation with Standard Delay Format (SDF) back annotation of the gate delays isdone according to Vachoux [5], Section 2.3 using Mentor Graphics ModelSim. A new histogram_top_syn entitywith accompagnying testbench tb_histogram_top_syn needs to created as modified versions ofhistogram_top and tb_histogram_top, which now instantiate the synthesised histogram calculation block.The region, to which the SDF file SYN/TIM/histogram_WIDTH320_HEIGHT240_NBITS_PIXEL8_NBITS_HISTOGRAM18_clock10ns_share_mapped.sdf needs to be mapped, is dut:histogram_1 and should beentered in the SDF tab of the Start Simulation dialog of Mentor Graphics ModelSim.3.3. Session 3: Placement & Routing of the Histogram BlockThe placement and routing of the gate-level netlist of the histogram block will be done accordingto the description in Vachoux [5], Chapter 4 using Cadence First Encounter. A Tcl script PAR/BIN/histogram_par.tcl (Listing 6, downloadable from the Moodle site) can be used to automatise theplacement and routing. Before it can be executed, an Encounter input configuration file PAR/CONF/histogram_WIDTH320_HEIGHT240_NBITS_PIXEL8_NBITS_HISTOGRAM18.conf needs to be created usingthe Design Import. . . Dialog from the File menu of Cadence Encounter as described in Vachoux [5],Section 4.2. An IO file (Listing 5, downloadable from the Moodle site) PAR/CONF/histogram_WIDTH320_HEIGHT240_NBITS_PIXEL8_NBITS_HISTOGRAM18.io controls the placement of the pins and prevents theirplacement on one of the power ring segments, which would lead to Design Rule Checker (DRC) errors. Torun the Tcl script, execute the following command in a Unix shell from the IPS/ project directory:[13]edatp1@immsunsrv2-IPS> encounter -log PAR/LOG/encounter -overwrite \-init PAR/BIN/histogram_par.tcl -winThe Tcl script can serve as a template for placement and routing scripts for other digital blocks.The post-placement-and-routing simulation with SDF back annotation of the gate delays is done accordingto Vachoux [5], Section 2.4 using the Verilog module of the histogram block generated by Cadence FirstEncounter. A new histogram_top_par entity with accompagnying testbench tb_histogram_top_par needs tocreated as modified versions of histogram_top and tb_histogram_top, which now instantiate the placed androuted histogram calculation block. The region, to which the SDF file PAR/TIM/histogram_WIDTH320_HEIGHT240_NBITS_PIXEL8_NBITS_HISTOGRAM18_clock10ns_cts-routed.sdf needs to be mapped, isdut:histogram_1 and should be entered in the SDF tab of the Start Simulation dialog of MentorGraphics ModelSim.A. Single Port Random Access Memory (RAM)Listing 1: VHDL source code of the Single Port RAM1 -- -----------------------------------------------------------------------------2 -- Title : Synchronous Single Port RAM3 -- Project : Image Processing System ( IPS )4 -- -----------------------------------------------------------------------------5 -- File : single_port_ram . vhd6 -- Author : Torsten Maehne < torsten . maehne@epfl .ch >7 -- Company : EPFL / STI / IMM / LSM8 -- Created : 2007 -03 -209 -- Last update : 2007 -03 -2210 -- Platform : ModelSim 6.2 d11 -- Standard : VHDL ’93/02 , Math Packages12 -- Depends :13 -- -----------------------------------------------------------------------------14 -- Description :15 -- The behaviour of the single port RAM is implemented using a synchronous16 -- process with asynchronous active - low reset . If the RAM is enabled with17 -- enable = ’1’ and rw_select = ’0’, then a data word is read from the6 Rev: 3, March 27, 2007 vlsi2semicustomtutorial.tex
18 -- specified address at each positive clock edge and output at data_out . If the19 -- RAM is enabled with enable = ’1’ and rw_select = ’1’, then the data from20 -- data_in is written to the specified address at each positive clock edge .21 -- -----------------------------------------------------------------------------22 -- Copyright (c) 2007 EPFL / STI / IMM / LSM23 -- -----------------------------------------------------------------------------24 -- Revisions : $Id : single_port_ram . vhd 2 2007 -03 -27 13:10:06 Z maehne $25 -- Date Version Author Description26 -- 2007 -03 -20 1.0 maehne Created27 -- -----------------------------------------------------------------------------2829 library ieee ;30 use ieee . std_logic_1164 . all ;31 use ieee . numeric_std . all ;3233 -- -----------------------------------------------------------------------------3435 entity single_port_ram is3637 generic (38 NBITS_WORD : positive := 8; -- bits of a word39 SIZE : positive := 256; -- number of words40 NBITS_ADDRESS : positive := 8); -- bits of address4142 port (43 signal clock : in std_logic ; -- clock input44 signal reset : in std_logic ; -- asynchronous reset ( active low )45 signal enable : in std_logic ; -- enable RAM operation46 signal rw_select : in std_logic ; -- select read ’0’ or write ’1’ mode47 signal address : in std_logic_vector ( NBITS_ADDRESS - 1 downto 0); -- ↵address to read from or write to48 signal data_in : in std_logic_vector ( NBITS_WORD - 1 downto 0); -- data ↵input49 signal data_out : out std_logic_vector ( NBITS_WORD - 1 downto 0)); -- ↵data output5051 end entity single_port_ram ;5253 -- -----------------------------------------------------------------------------5455 architecture behavioural of single_port_ram is5657 begin -- architecture behavioural5859 -- purpose : control the read and write process to the RAM60 -- type : sequential61 -- inputs : clock , reset , enable , rw_select , address62 -- outputs : data_out63 ram_control : process ( clock , reset ) is64 type word_vector is array ( natural range ) of ↵std_logic_vector ( NBITS_WORD - 1 downto 0);65 variable memory : word_vector (0 to SIZE - 1) := ( others => ( others => ↵’0’)); -- memory66 begin -- process ram_fsm67 if reset = ’0’ then -- asynchronous reset ( active low )68 memory := ( others => ( others => ’0’));69 data_out ’0’);70 elsif clock ’ event and clock = ’1’ then -- rising clock edge71 if enable = ’1’ and rw_select = ’0’ then -- read from RAM72 data_out
Page 1 and 2: EPFL/STI/IMM/LSMBâtiment ELD, Stat
Page 3 and 4: Table 1: Interface of the Random Ac
Page 5: eset = 0START PIXELframe start = 1
Page 9 and 10: 50 -- component generics51 constant
Page 11 and 12: 2425 library ieee ;26 use ieee . st
Page 13 and 14: 36 set NBITS_PIXEL 837 set NBITS_HI
Page 15 and 16: 158 compile159 } else { compile -ma
Page 17 and 18: 69 Pin: ram_data_in [16] n70 Pin: r
Page 19 and 20: 86 # if 1, create a clock tree spec
Page 21 and 22: 210211 # --------------------------
Page 23 and 24: 334 # -----------------------------

Tutorial for the Semi Custom Part of the Image Processing System

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