Tutorial for the Semi Custom Part of the Image Processing System

158 compile159 } else { compile -map_effort medium -area_effort medium160 ungroup -all -flatten161 compile -incremental -map_effort high162 }163164 # -----------------------------------------------------------------------------165 # Save mapped design166 # -----------------------------------------------------------------------------167 write -hierarchy -format $DB_FORMAT -output $DB_MAPPED_FILE168169 # -----------------------------------------------------------------------------170 # Generate reports171 # -----------------------------------------------------------------------------172 report_area -nosplit > $RPT_AREA_FILE173 report_timing -path full \174 -delay max \175 -nworst 1 \176 -max_paths 1 \177 -significant_digits 2 \178 -nosplit \179 -sort_by group \180 > $RPT_TIMING_FILE181 report_resources -nosplit -hierarchy > $RPT_RESOURCES_FILE182 report_reference -nosplit > $RPT_REFERENCES_FILE183 report_cell -nosplit > $RPT_CELLS_FILE184185 # -----------------------------------------------------------------------------186 # Generate VHDL netlist187 # -----------------------------------------------------------------------------188 change_names -rule vhdl -hierarchy -verbose189 write -format vhdl -hierarchy -output $VHDL_NETLIST_FILE190191 # -----------------------------------------------------------------------------192 # Generate SDF data193 # -----------------------------------------------------------------------------194 write_sdf -version 2.1 $SDF_FILE195196 # -----------------------------------------------------------------------------197 # Generate Verilog netlist198 #199 # The design is reloaded from scratch to avoid potential naming problems200 # when using the netlist for placement and routing201 # -----------------------------------------------------------------------------202 remove_design -all203 read_file -format $DB_FORMAT $DB_MAPPED_FILE204 change_names -rule verilog -hierarchy -verbose205 write -format verilog -hierarchy -output $VLOG_NETLIST_FILE206207 # -----------------------------------------------------------------------------208 # Save system constraints209 # -----------------------------------------------------------------------------210 write_sdc -nosplit $SDC_FILEListing 5: Cadence First Encounter IO assignment file for the histogram calculation block1 # #####################################################2 # #3 # Cadence Design Systems, Inc. #4 # Cadence (R) Encounter (TM) IO Assignments #5 # #6 # #####################################################vlsi2semicustomtutorial.tex Rev: 3, March 27, 2007 15