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Tutorial for the Semi Custom Part of the Image Processing System

Tutorial for the Semi Custom Part of the Image Processing System

Tutorial for the Semi Custom Part of the Image Processing System

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210211 # -----------------------------------------------------------------------------212 # Define global Power nets - make global connections213 # -----------------------------------------------------------------------------214 clearGlobalNets215 globalNetConnect vdd ! -type pgpin -pin vdd ! -inst * -module {} -verbose216 globalNetConnect gnd ! -type pgpin -pin gnd ! -inst * -module {} -verbose217 # globalNetConnect vdd3o ! -type pgpin -pin vdd3o ! -inst * -module {} -verbose218 # globalNetConnect vdd3r1 ! -type pgpin -pin vdd3r1 ! -inst * -module {} -verbose219 # globalNetConnect vdd3r2 ! -type pgpin -pin vdd3r2 ! -inst * -module {} -verbose220 # globalNetConnect gnd3o ! -type pgpin -pin gnd3o ! -inst * -module {} -verbose221 # globalNetConnect gnd3r ! -type pgpin -pin gnd3r ! -inst * -module {} -verbose222223 # -----------------------------------------------------------------------------224 # Initialize floorplan225 # -----------------------------------------------------------------------------226 floorPlan -r $FP_ASPECT_RATIO \227 $FP_ROW_DENSITY \228 $FP_CORE2IO $FP_CORE2IO $FP_CORE2IO $FP_CORE2IO229 fit230 saveDesign $SAVE_DESIGN_FP_FILE231232 # -----------------------------------------------------------------------------233 # Create and route power rings and power stripes234 # -----------------------------------------------------------------------------235 addRing \236 -around core \237 -nets { gnd ! vdd ! } \238 -width_bottom $PR_WIDTH -width_top $PR_WIDTH \239 -width_left $PR_WIDTH -width_right $PR_WIDTH \240 -spacing_bottom $PR_SPACING -spacing_top $PR_SPACING \241 -spacing_left $PR_SPACING -spacing_right $PR_SPACING \242 -layer_bottom $PR_LAYER_TB -layer_top $PR_LAYER_TB \243 -layer_left $PR_LAYER_LR -layer_right $PR_LAYER_LR \244 -center 1 \245 -tl 1 -tr 1 -bl 1 -br 1 -lt 1 -lb 1 -rt 1 -rb 1 \246 -stacked_via_bottom_layer MET1 -stacked_via_top_layer MET4 \247 -threshold 0.7248 if { $ADD_STRIPES } {249 addStripe \250 -nets { gnd ! vdd ! } \251 -number_<strong>of</strong>_sets $ST_NUM_SETS \252 -spacing $ST_SPACING \253 -layer $ST_LAYER_V \254 -width $ST_WIDTH \255 -xleft_<strong>of</strong>fset $ST_XOFS_L256 }257 sroute \258 -jogControl { preferWithChanges differentLayer } \259 -nets { gnd ! vdd ! }260 saveDesign $SAVE_DESIGN_PR_FILE261262 # -----------------------------------------------------------------------------263 # Add CAP cells264 # -----------------------------------------------------------------------------265 addEndCap -preCap ENDCAPL -postCap ENDCAPR -prefix ENDCAP266267 # -----------------------------------------------------------------------------268 # Core cell placement269 # -----------------------------------------------------------------------------270 if { $PLACE_TIMING } {271 amoebaPlace $PL_EFFORT -timingdrivenvlsi2semicustomtutorial.tex Rev: 3, March 27, 2007 21

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