FPGA a:nd CPLD Architectures: A Tutorial - IEEE Design & Test of ...

short wire segments that span a single
CLB (the number of segments in each
channel varies for each member of the
XC4000 family), longer segments that
span two CLBs, and very long segments
that span the chip’s entire length or
width. Programmable switches are
available (see Figure 5) to connect CLB
inputs and outputs to the wire segments
or to connect one wire segment to an-
other. A small section of an XC4000
routing channel appears in Figure 19.
The figure shows only the wire seg-
ments in a horizontal channel-not the
vertical routing channels, CLB inputs
and outputs, and the routing switches.
An important point about the Xilinx in-
terconnect is that signals must pass
through switches to reach one CLB
from another, and the total number of
switches traversed depends on the par-
ticular set of wire segments used. Thus,
an implemented circuit’s speed perfor-
mance depends in part on how CAD
tools allocate the wire segments to in-
dividual signals.
Altera Flex 8000 and Flex 10K.
Altera’s Flex 8000 series combines
FPGA and CPLD technologies. The de-
vices consist of a three-level hierarchy
much like that of CPLDs. However, the
lowest level of the hierarchy is a set of
lookup tables, rather than an SPLDlike
block, and so we categorize the Flex
8000 as an FPGA. The SRAM-based Flex
8000 features a four-input lookup table
as its basic logic block. Logic capacity
of the 8000 series ranges from about
4,000 to more than 15,000 gates.
Figure 20 illustrates the overall Flex
8000 architecture. The basic logic
block, called a logic element, contains
a four-input lookup table, a flip-flop,
and special-purpose carry circuitry for
arithmetic circuits (similar to the Xilinx
XC4000). The logic element also in-
cludes cascade circuitry that allows ef-
ficient implementation of wide AND
functions. Figure 21 shows details of the
logic element.
SUMMER 1996
Logic array block i
Figure 20. Ahera Flex 8000 architecture.
Figure 2 I. Flex 8000 logic element.
This design groups logic elements into
sets of eight, called logic array blocks (a
term borrowed from Altera’s CPLDs). As
shown in Figure 22 on the next page,
each logic array block contains local in-
terconnection, and each local wire can
connect any logic element to any other
logic element within the same logic ar-
ray block. The local interconnect also
connects to the Flex 8000’s FastTrack
global interconnect. Like the long wires
n...nn...n n...n
in the Xllinx XC4000, each FastTrack wire
extends the full width or height of the de
vice. However, a major difference be-
tween Flex 8000 and Xilinx chips is that
FastTrack consists only of long lines,
making the Flex 8000 easy for CAD tools
to configure automatically. All FastTrack
horizontal wires are identical. Therefore,
interconnect delays in the Flex 8000 are
more predictable than in FPGAs that
employ many shorter segments because
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