02.12.2012 Views

FPGA a:nd CPLD Architectures: A Tutorial - IEEE Design & Test of ...

FPGA a:nd CPLD Architectures: A Tutorial - IEEE Design & Test of ...

FPGA a:nd CPLD Architectures: A Tutorial - IEEE Design & Test of ...

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

Switch type Reprogramma ble? Volatile? Technology<br />

Fuse<br />

EPROM<br />

EEPROM<br />

S M<br />

Anti fuse<br />

No<br />

Yes<br />

(out <strong>of</strong> circuit)<br />

Yes<br />

(in circuit)<br />

Yes<br />

(in circuit)<br />

No<br />

are floating gate transistors like those<br />

used in EPROM (erasable programma-<br />

ble read-only memoiy) a<strong>nd</strong> EEPROM<br />

(electrically erasable PROM). For<br />

<strong>FPGA</strong>s, they are SRAM (static RAM) a<strong>nd</strong><br />

antifuse. Table 1 lists the most impor-<br />

tant characteristics <strong>of</strong> these program-<br />

ming technologies.<br />

To use an EPROM or EEPROM tran-<br />

sistor as a programmable switch for<br />

<strong>CPLD</strong>s (a<strong>nd</strong> many SPLDs), the manu-<br />

facturer places the transistor between<br />

two wires to facilitate implementation<br />

<strong>of</strong> wired-AND functions. Figure 4 shows<br />

EPROM transistors connected in a<br />

<strong>CPLD</strong>’s AND plane. An input to the AND<br />

plane can drive a product wire to logic<br />

level 0 through an EPROM transistor, if<br />

that input is part <strong>of</strong> the correspo<strong>nd</strong>ing<br />

product term. For inputs not involved<br />

in a product term, the appropriate<br />

EPROM transistors are programmed as<br />

permanently turned <strong>of</strong>f. The diagram <strong>of</strong><br />

an EEPROM-based device would look<br />

similar to the one in Figure 4.<br />

Although no technical reason pre-<br />

vents application <strong>of</strong> EPROM or EEP-<br />

ROM to <strong>FPGA</strong>s, current commercial<br />

<strong>FPGA</strong> products use either SRAM or an-<br />

tifuse technologies. The example <strong>of</strong><br />

SRAM-controlled switches in Figure 5 il-<br />

lustrates two applications, one to con-<br />

trol the gate nodes <strong>of</strong> pass-transistor<br />

switches a<strong>nd</strong> the other, the select lines<br />

<strong>of</strong> multiplexers that drive logic block in-<br />

puts. The figure shows the connection<br />

<strong>of</strong> one logic block (represented by the<br />

SUMMER 1996<br />

Product<br />

No Bipolar wire<br />

No UVCMOS<br />

No EECMOS<br />

Yes CMOS I<br />

I<br />

I EPROM I EPROM<br />

CMOS+ Figure 4. EPROM programmable<br />

switches.<br />

7 I I- I<br />

I I I<br />

I I I<br />

Figure 5. SRAM-controlled programmable switches.<br />

AND gate in the upper left comer) to an-<br />

other through two pass-transistor<br />

switches a<strong>nd</strong> then a multiplexer, all<br />

controlled by SRAM cells. Whether an<br />

<strong>FPGA</strong> uses pass transistors, multiplex-<br />

ers, or both depe<strong>nd</strong>s on the particular<br />

product.<br />

Antifuses are originally open circuits<br />

that take on low resistance only when<br />

programmed. Antifuses are manufac-<br />

tured using modified CMOS technolo-<br />

gy. As an example, Figure 6 (next page)<br />

depicts Actel’s PLICE (programmable<br />

logic interconnect circuit element), an<br />

tifuse structure.’ The antifuse, posi-<br />

tioned between two interconnect wires,<br />

consists <strong>of</strong> three sa<strong>nd</strong>wiched layers:<br />

co<strong>nd</strong>uctors at top a<strong>nd</strong> bottom a<strong>nd</strong> an<br />

insulator in the middle. Unpro-<br />

grammed, the insulator isolates the top<br />

a<strong>nd</strong> bottom layers; programmed, the in-<br />

sulator becomes a low-resistance link.<br />

11<br />

I<br />

45

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!