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FPGA a:nd CPLD Architectures: A Tutorial - IEEE Design & Test of ...

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Roc. <strong>Design</strong> Automation Conference PAC),<br />

<strong>IEEE</strong> CS Press.<br />

<strong>FPGA</strong> Symp. Series: Third Int’l ACM Symp.<br />

Field-Programmable Gate Arrays (<strong>FPGA</strong><br />

95) a<strong>nd</strong> Fourth Int’l ACMSymp. Field-Pro-<br />

grammable Gate Arrays (EPGA 961,<br />

Assoc. for Computing Machinery, New<br />

York.<br />

Stephen Brown is an assistant pr<strong>of</strong>essor <strong>of</strong><br />

electrical a<strong>nd</strong> computer engineering at the<br />

University <strong>of</strong> Toronto. He holds a PhD in<br />

electrical engineering from that university;<br />

his dissertation (on architecture a<strong>nd</strong> CAD<br />

for <strong>FPGA</strong>s) won him the Canadian NSERC‘s<br />

1992 prize for the best doctoral thesis in<br />

Canada. In 1990, the International Confer-<br />

ence on Computer-Aided <strong>Design</strong> awarded<br />

him a<strong>nd</strong> coauthor Jonathan Rose a Best Pa-<br />

per award. A coauthor <strong>of</strong> the book Field-<br />

Programmable Gate Arrays, he has also won<br />

four awards for excellence in teaching elec-<br />

trical engineering, computer engineering,<br />

a<strong>nd</strong> computer science courses. Brown is<br />

the general a<strong>nd</strong> program chair for the<br />

Fourth Canadian Workshop on Field-Pro-<br />

grammable Devices (FPD 96), a<strong>nd</strong> is on the<br />

Technical Program Committee for the Sixth<br />

International Workshop on Field-Program-<br />

mable Logic (FPL 96). He is a member <strong>of</strong><br />

the <strong>IEEE</strong> a<strong>nd</strong> the Computer Society.<br />

Jonathan Rose is an associate pr<strong>of</strong>essor<br />

<strong>of</strong> electrical a<strong>nd</strong> computer engineering at<br />

the University <strong>of</strong> Toronto. His research in-<br />

terests are in the area <strong>of</strong> architecture a<strong>nd</strong><br />

CAD for field-programmable gate arrays<br />

a<strong>nd</strong> systems. He coauthored the book Field-<br />

Programmable Gate Arrays. Rose holds a<br />

PhD in electrical engineering from the Uni-<br />

versity <strong>of</strong> Toronto. He is the general chair<br />

<strong>of</strong> the Fourth International Symposium on<br />

<strong>FPGA</strong>s (<strong>FPGA</strong> 96) a<strong>nd</strong> serves on the tech-<br />

nical program committee for the Sixth<br />

International Workshop on Field-Program-<br />

mable Logic. In 1990, ICCAD awarded him<br />

a<strong>nd</strong> coauthor Stephen Brown a Best Paper<br />

award. He is a member <strong>of</strong> the <strong>IEEE</strong>, the<br />

Computer Society, the Association for<br />

Computing Machinery, a<strong>nd</strong> SIGDA.<br />

Direct questions concerning this article<br />

to Stephen Brown, Dept. <strong>of</strong> Electrical a<strong>nd</strong><br />

Computer Engineering, Univ. <strong>of</strong> Toronto, 10<br />

Kings College Rd., Toronto, ONT, Canada<br />

M5S 3G4; brown@eecg.toronto.edu.<br />

CALL FOR ARTICLES<br />

<strong>IEEE</strong> <strong>Design</strong> & <strong>Test</strong> <strong>of</strong> Computers<br />

Special Issue on Microprocessors<br />

D&T focuses on practical articles <strong>of</strong> near-term interest<br />

to the pr<strong>of</strong>essional engineering community. D&Tseeks ar-<br />

ticles <strong>of</strong> significant contribution that address the design,<br />

test, debugging, manufacturability, a<strong>nd</strong> yield improvement<br />

<strong>of</strong> microprocessors a<strong>nd</strong> microcontrollers. The areas <strong>of</strong> in-<br />

terest include but are not limited to<br />

@ Circuit design a<strong>nd</strong> design methodologies<br />

b Logic design a<strong>nd</strong> design methodologies<br />

@ CAD tools a<strong>nd</strong> methodologies<br />

@ <strong>Design</strong>-for-test techniques a<strong>nd</strong> applications<br />

e Debugging experiences, tools, a<strong>nd</strong> methodologies<br />

@ Yield improvement experiences, tools, a<strong>nd</strong><br />

methodologies<br />

# Project management<br />

SUMMER 1996<br />

Interested authors should submit four copies <strong>of</strong> a double<br />

spaced manuscript no longer than 35 pages, in English, by<br />

June 15, 1996. Each copy must contain contact informa-<br />

tion (name, postal a<strong>nd</strong> e-mail addresses, a<strong>nd</strong> phone/fax<br />

numbers). Final articles will be due October 15, 1996.<br />

For author guidelines, see D&T’sSpring 1996 issue or Web<br />

page at http://www.computer.org/pubs/d&t/d&t.htm.<br />

Submit manuscripts to:<br />

Marc E. Levitt<br />

Special Issue Guest Editor<br />

Sun Microelectronics, USUN02-301<br />

2550 Garcia Avenue, Mountain View, CA 94043<br />

phone (408) 774-8268; fax (408) 774-2099<br />

marc.leviM?eng.sun.com<br />

57

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