PIC24FJ64GA004 Family Silicon Errata and Data Sheet ... - Microchip

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PIC24FJ64GA004 FAMILY21. Module: I/O PortsThe I/O pin outputs, VOL and VOH, meet thespecifications in Table 3 below.Work aroundNone.Affected Silicon RevisionsA3/A4B4 B5 B8XTABLE 3:DC CHARACTERISTICSDC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONSStandard Operating Conditions: 2.0V to 3.6V (unless otherwise stated)Operating temperature -40°C TA +85°C for IndustrialParamNo.Sym Characteristic Min Typ (1) Max Units ConditionsVOL Output Low VoltageDO10 All I/O Pins — — .55 V IOL = 8.5 mA, VDD = 3.6V— — .4 V IOL = 7.8 mA, VDD = 3.6V— — .55 V IOL = 6.0 mA, VDD = 2.0V— — .4 V IOL = 5.0 mA, VDD = 2.0VVOH Output High VoltageDO20 All I/O Pins 3.0 — — V IOH = -3.0 mA, VDD = 3.6V2.4 — — V IOH = -6.0 mA, VDD = 3.6V1.65 — — V IOH = -1.0 mA, VDD = 2.0V1.4 — — V IOH = -3.0 mA, VDD = 2.0VNote 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance onlyand are not tested.DS80470G-page 10 2009-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY22. Module: I/O PortsDuring Power-on Reset (POR), the device maydrive the OSCO/RA3 pin as a clock out output forapproximately 20 S. During this time, the pin willbe driven high and low rather than being set tohigh-impedance. This may cause issues ondesigns that use the pin as a general purpose I/O.Designs should be reviewed to ensure that theirintended operation will not be disrupted if the pin isdriven during POR.Work aroundNone.Affected Silicon RevisionsA3/A4X23. Module: JTAGWhen entering the SHIFT_DR state while inICSP Communications mode, an extra clockedge may be generated, causing JTAG and ICSPcommunications to lose synchronization. Thisprevents device programming using ICSP overJTAG. JTAG boundary scan is not affected andoperates as expected.Work aroundNone.Affected Silicon RevisionsA3/A4XB4 B5 B8B4 B5 B824. Module: RTCCWhen performing writes to the ALCFGRPT register,some bits may become corrupted. The erroroccurs because of desynchronization between theCPU clock domain and the RTCC clock domain.The error causes data, from the instructionfollowing the ALCFGRPT instruction, to overwritethe data in ALCFGRPT.Work aroundAlways follow writes to the ALCFGRPT registerwith an additional write of the same data to adummy location. These writes can be performed toRAM locations, W registers or unimplementedSFR space.The optimal way to perform the work around:1. Read ALCFGRPT into a RAM location.2. Modify the ALCFGRPT data, as required, inRAM.3. Move the RAM value into ALCFGRPT and adummy location, in back-to-back instructions.Affected Silicon RevisionsA3/A4X25. Module: I 2 CB4 B5 B8When the I 2 C module is operating in Slave mode,after the ACKSTAT bit is set when receiving aNACK from the master, it may be cleared by thereception of a Start or Stop bit.Due to this issue, the state of ACKSTAT, after atransmission finishes, will vary depending on thedevice revision. On revisions with this issue,ACKSTAT will be clear at the end of the transmission,and will remain clear until the next NACK isreceived from the Master. On revisions without theissue, ACKSTAT will be set at the end of a transmissionand will remain set until receiving an ACKfrom the Master.Work aroundStore the value of the ACKSTAT bit immediatelyafter receiving a NACK from the master.Affected Silicon RevisionsA3/A4XB4 B5 B8 2009-2013 Microchip Technology Inc. DS80470G-page 11
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