PIC24FJ64GA004 Family Silicon Errata and Data Sheet ... - Microchip

PIC24FJ64GA004 FAMILY42. Module: Core (Code Protection)When General Segment Code Protection hasbeen enabled (GCP Configuration bit is programmed),applications are unable to write to thefirst 512 bytes of the program memory space(0000h through 0200h). In applications that mayrequire the interrupt vectors to be changed duringrun time, such as bootloaders, modifications to theInterrupt Vector Tables (IVTs) will not be possible.Work aroundCreate two new Interrupt Vector Tables, one eachfor the IVT and AIVT, in an area of program spacebeyond the affected region. Map the addresses inthe old vector tables to the new tables. These newtables can then be modified as needed to theactual addresses of the ISRs.Affected Silicon RevisionsA3/A4B4 B5 B8X44. Module: UART (IrDA ® )When IrDA reception is enabled(UxMODE = 1), the operation of the RXINVbit (UxMODE) is the opposite of its descriptionin the device data sheet (DS39881D); that is,setting the bit configures the module for a logichigh Idle state, and clearing the bit configures themodule for a logic low Idle state. Using the bit asdescribed in the data sheet may result inreception errors.Work aroundInvert the state of the RXINV bit. If the Idle state ofthe received signal is logic high, set RXINV = 1. Ifthe Idle state of the received signal is logic low,clear RXINV.Affected Silicon RevisionsA3/A4XB4 B5 B843. Module: SPISPIx operating in Enhanced Buffer mode(SPIBEN = 1) may set the interrupt flag, SPIxIF,before the last bit has been transmitted from theShift register. This issue only affects one of theeight Interrupt modes, SISEL = 101,which generates an interrupt when the last bithas shifted out of the Shift register, indicating thetransfer is complete. All other Interrupt modes inEnhanced Buffer mode work as described in theproduct data sheet.Work aroundMultiple work arounds are available. Selectanother Buffer Interrupt mode using theSISEL bits in the SPIxSTAT register. Acomparable mode is to generate an interruptwhen the FIFO is empty, SISEL = 110.Another option is to monitor the SRMPT bit(SPIxSTAT) to determine when the Shiftregister is empty.Affected Silicon Revisions45. Module: CoreOperations that immediately follow any manipulationsof the DOZE or DOZEN bits(CLKDIV) may not execute properly. Inparticular, for instructions that operate on anSFR, data may not be read properly. Also, bitsautomatically cleared in hardware may not becleared if the operation occurs during this interval.Work aroundAlways insert a NOP instruction before and aftereither of the following:• Enabling or disabling Doze mode by settingor clearing the DOZEN bit.• Before or after changing the DOZEbits.Affected Silicon RevisionsA3/A4B4 B5 B8X X X XA3/A4B4 B5 B8X X X XDS80470G-page 16 2009-2013 Microchip Technology Inc.