PIC24FJ64GA004 Family Silicon Errata and Data Sheet ... - Microchip

PIC24FJ64GA004 FAMILY14. Module: UARTWith the auto-baud feature selected, the Sync fieldcharacter (0x55) may be loaded into the FIFO asdata.Work aroundTo prevent the Sync field character from beingloaded into the FIFO, load the UxBRG register witheither 0x0000 or 0xFFFF prior to enabling theauto-baud feature (ABAUD = 1).Affected Silicon RevisionsA3/A4X15. Module: UARTThe auto-baud may miscalculate for certain baudrates and clock speed combinations, resulting in aBRG value that is 1 greater or less than theexpected value. When UxBRG is less than 50, thiscan result in transmission and reception failuresdue to introducing error greater than 1%.Work aroundTest auto-baud calculations at various clock speedand baud rate combinations that would be used inapplications. If an inaccurate UxBRG value is generated,manually correct the baud rate in user code.Affected Silicon RevisionsA3/A4X16. Module: UARTThe UART module will not generate consecutiveBreak characters. Trying to perform a back-tobackBreak character transmission will cause theUART module to transmit the dummy characterused to generate the first Break character,instead of transmitting the second Break character.Break characters are generated correctly ifthey are followed by non-Break charactertransmission.Work aroundNone.B4 B5 B8B4 B5 B8Affected Silicon Revisions17. Module: Output CompareIn PWM mode, the output compare module maymiss a compare event when the Current DutyCycle register (OCxRS) value is 0x0000 (0% dutycycle) and the OCxRS register is updated with avalue of 0x0001. The compare event is onlymissed the first time a value of 0x0001 is written toOCxRS and the PWM output remains low for onePWM period. Subsequent PWM high and lowtimes occur as expected.Work aroundIf the current OCxRS register value is 0x0000,avoid writing a value of 0x0001 to OCxRS.Instead, write a value of 0x0002. In this case, however,the duty cycle will be slightly different fromthe desired value.Affected Silicon RevisionsA3/A4X18. Module: SPIWhen using Enhanced Buffer mode, someindicator bits may be set at incorrect times:• For slave transfers, the SRMPT bit(SPIxSTAT) is set early, after only 7 SCKxperiods.• For Slave Interrupt modes (SISELx = 5), thereis a one SCKx period delay between theinterrupt event and the SPIxIF bit being set.• There may be several instruction cycle delaysbetween the FIFO full or FIFO empty eventsand the interrupt flags, or indicator bits beingset.Work aroundNone at this time.Affected Silicon RevisionsA3/A4XB4 B5 B8B4 B5 B8A3/A4B4 B5 B8X X X XDS80470G-page 8 2009-2013 Microchip Technology Inc.