PIC24FJ64GA004 Family Silicon Errata and Data Sheet ... - Microchip

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PIC24FJ64GA004 FAMILYTABLE 2:SPISPISPIModuleMastermodeMastermodeFramedmodes46. Spurious transmission and reception of nulldata on wake-up from Sleep (Master mode).47. Inaccurate SPITBF flag with high clockdivider.X X X XX X X48. Framed SPIx modes not supported. X X X XCore Data SRAM 49. Higher current consumption during SRAMoperations.I/O PortsA/DConverterPORTA andPORTB50. Some I/O pin functions do not work correctlyunder certain conditions— 51. Once the A/D module is enabled, it maycontinue to draw extra currentUART TX Interrupt 52. A TX Interrupt may occur before the datatransmission is complete.I 2 C SMBus 53. I2C1 may not function when I2C2 is inSMBus mode.Note 1:SILICON ISSUE SUMMARY (CONTINUED)FeatureItemNumberIssue SummaryOnly those issues indicated in the last column apply to the current silicon revision.Affected Revisions (1)A3/A4 B4 B5 B8XXX X X XX X X XX X XX X X XDS80470G-page 4 2009-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILYSilicon Errata IssuesNote:1. Module: JTAGWhen the JTAG is disabled, the pull-up resistor onthe TDI pin (Pin 35/RA9) will stay enabled on the44-pin variants of the device. This can cause thedevice to draw extra current when asleep if the pinis used as an input and held low.Work around:The pin will not draw extra current if any of thefollowing work around techniques are used:• The pin is used as an output.• The pin is driven high as an input.• JTAG is enabled.Affected Silicon RevisionsA3/A4X2. Module: Low-Voltage Detect (LVD)The Low-Voltage Detect interrupt will not occur ifthe device comes out of Reset in a low-voltagestate. To trigger an interrupt, the voltage mustdecrease to a low-voltage range while the deviceis running.Work aroundNone.Affected Silicon RevisionsA3/A4XThis document summarizes all siliconerrata issues from all revisions of silicon,previous as well as current. Only theissues indicated by the shaded column inthe following tables apply to the currentsilicon revision (B8).B4 B5 B8B4 B5 B83. Module: CoreIf a clock failure occurs when the device is in Idlemode, the oscillator failure trap does not vector tothe Trap Service Routine. Instead, the device willsimply wake-up from Idle mode and continue codeexecution if the Fail-Safe Clock Monitor (FSCM) isenabled.Work aroundWhenever the device wakes up from Idle (assumingthe FSCM is enabled), the user software shouldcheck the status of the OSCFAIL bit (INTCON1)to determine whether a clock failure occurred, andthen perform an appropriate clock switch operation.Affected Silicon RevisionsA3/A4XB4 B5 B84. Module: CoreIf a RAM read is performed on the instructionimmediately prior to enabling Doze mode, then anextra read event will occur when Doze mode isenabled. On most SFRs and on user RAM space,this will have no visible effect. However, this cancause registers which perform actions on reads,such as auto-incrementing or decrementing apointer or removing data from a FIFO buffer, torepeat that action, possibly resulting in lost data.Work aroundOn the instruction prior to entering Doze mode, besure not to read a register which performs a secondaryaction. Examples of this would be UARTand SPIx FIFO buffers, and the RTCVAL registers.The easiest way to ensure this does not occur is toexecute a NOP instruction before entering Dozemode.Affected Silicon RevisionsA3/A4XB4 B5 B8 2009-2013 Microchip Technology Inc. DS80470G-page 5
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