PIC24FJ64GA004 Family Silicon Errata and Data Sheet ... - Microchip

PIC24FJ64GA004 FAMILYTABLE 2:RTCC — 24. Write errors to ALCFGRPT register. XI 2 C Slave mode 25. In Slave mode, ACKSTAT bit state change. XI 2 C — 26. Issues with write operations on I2CxSTAT. XUART IrDA ® 27. IR baud clock only available during transmit. XI/O PPS 28. Issues with digital signal priorities with RP12 Xand RP18.UART UERIF 29. No UERIF flag with multiple errors. X X X XInterruptUART FIFO Error 30. PERR and FERR are not correctly set for all X X X XFlagsbytes in receive FIFO.Core BOR 31. Spontaneous BOR events with low-rangeVDD.X X X XCoreInstructionSet32. Loop count errors with REPEAT instructionand R-A-W stalls.Memory PSV 33. False address error traps at lower boundaryof PSV space.RTCC — 34. Decrement of alarm repeat counter undercertain conditions.SPIModuleI 2 CSILICON ISSUE SUMMARY (CONTINUED)MastermodeMastermode35. SPIF and SPIBEN may become set earlyunder certain conditions.36. Module may respond to its own mastertransmission as a slave under certainconditions.XX X XX X XXX X X XI 2 C Slave mode 37. Failure to respond correctly to someX X X Xreserved addresses in 10-bit mode.I 2 C — 38. TBF flag not cleared under certainXconditions.UART — 39. Erroneous sampling and framing errors X X X Xwhen using two Stop bits.Oscillator SOSC 40. Low-power SOSC unimplemented. XVoltage — 41. Standby mode not available. XRegulatorCore Code-Protect 42. General code protection disablesXbootloader functionality.SPIx — 43. Interrupts when SPIx is operating inX X X XEnhanced Buffer mode.UART IrDA ® 44. RXINV bit operation is inverted in IrDA ® XmodeCore Doze Mode 45. Instruction execution glitches followingDOZE bit changes.X X X XNote 1:FeatureItemNumberIssue SummaryOnly those issues indicated in the last column apply to the current silicon revision.Affected Revisions (1)A3/A4 B4 B5 B8 2009-2013 Microchip Technology Inc. DS80470G-page 3