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PIC24FJ64GA004 Family Silicon Errata and Data Sheet ... - Microchip

PIC24FJ64GA004 Family Silicon Errata and Data Sheet ... - Microchip

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<strong>PIC24FJ64GA004</strong> FAMILY30. Module: UART (FIFO Error Flags)Under certain circumstances, the PERR <strong>and</strong>FERR error bits may not be correct for all bytes inthe receive FIFO. This has only been observedwhen both of the following conditions are met:• the UART receive interrupt is set to occur whenthe FIFO is full or 3/4 full (UxSTA = 1x),<strong>and</strong>• more than 2 bytes with an error are received.In these cases, only the first two bytes, with aparity or framing error, will have the correspondingbits indicate correctly. The error bits will not be setafter this.Work aroundNone.Affected <strong>Silicon</strong> RevisionsA3/A4B4 B5 B8X X X X32. Module: Core (Instruction Set)If an instruction producing a read-after-write stallcondition is executed inside a REPEAT loop, theinstruction will be executed fewer times than wasintended. For example, this loop:repeat #0xfinc [w1],[++w1]will execute less than 16 times.Work aroundAvoid using REPEAT to repetitively executeinstructions that create a stall condition. Instead,use a software loop using conditional branches.The MPLAB ® C Compiler will not generateREPEAT loops that cause this erratum.Affected <strong>Silicon</strong> RevisionsA3/A4XB4 B5 B831. Module: Core (BOR)When the on-chip regulator is enabled (DISVREGtied to VSS), a BOR event may spontaneouslyoccur under the following circumstances:• VDD is less than 2.5V, <strong>and</strong>• the internal b<strong>and</strong> gap reference is being used asa reference with the A/D Converter(AD1PCFG = 0)Work aroundDo not select the internal b<strong>and</strong> gap as a referencefor the A/D Converter when the on-chip regulatoris in Tracking mode (LVDIF (IFS4) = 1).Affected <strong>Silicon</strong> RevisionsA3/A4B4 B5 B8X X X X33. Module: Memory (Program SpaceVisibility)When accessing data in the PSV area of dataRAM, it is possible to generate a false addresserror trap condition by reading data locatedprecisely at the lower address boundary (8000h).If data is read using an instruction with an autodecrement,the resulting RAM address will bebelow the PSV boundary (i.e., at 7FFEh); this willresult in an address error trap.This false address error can also occur if a 32-bitMOV instruction is used to read the data at location,8000h.Work aroundDo not use the first location of a PSV page(address 8000h).The MPLAB C Compiler (v3.11 or later) supportsthe option, -merrata=psv_trap, to prevent itfrom generating code that would cause thiserratum.Affected <strong>Silicon</strong> RevisionsA3/A4B4 B5 B8X X X 2009-2013 <strong>Microchip</strong> Technology Inc. DS80470G-page 13

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