PIC24FJ64GA004 Family Silicon Errata and Data Sheet ... - Microchip

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PIC24FJ64GA004 FAMILY34. Module: RTCCUnder certain circumstances, the value of theAlarm Repeat Counter (ALCFGRPT) may beunexpectedly decremented. This happens onlywhen a byte write to the upper byte of ALCFGRPTis performed in the interval between a device POR/BOR and the first edge from the RTCC clocksource.Work aroundDo not perform byte writes on ALCFGRPT,particularly the upper byte.Alternatively, wait until one period of the SOSChas completed before performing byte writes toALCFGRPT.Affected Silicon RevisionsA3/A4B4 B5 B8X X X35. Module: SPI (Master Mode)In Master mode, the SPIx Interrupt Flag (SPIxIF)and the SPIRBF bit (SPIxSTAT) may bothbecome set one-half clock cycle early, instead ofon the clock edge. This occurs only under thefollowing circumstances:• Enhanced Buffer mode is disabled(SPIBEN = 0); and• the module is configured for serial data outputchanges on transition from clock active to clockIdle state (CKE = 1).If the application is using the interrupt flag todetermine when data to be transmitted is written tothe transmit buffer, the data currently in the buffermay be overwritten.Work aroundBefore writing to the SPIx buffer, check the SCKx pinto determine if the last clock edge has passed.Example 1 (below) demonstrates a method for doingthis. In this example, the RD1 pin functions as theSPIx clock, SCKx, which is configured as Idle low.Affected Silicon Revisions36. Module: I 2 C (Master Mode)Under certain circumstances, a module operatingin Master mode may Acknowledge its own commandaddressed to a slave device. This happenswhen the following occurs:• 10-Bit Addressing mode is used (A10M = 1);and• the I 2 C master has the same two upperaddress bits (I2CADD) as the addressedslave module.In these cases, the master also Acknowledges theaddress command and generates an erroneous I 2 Cslave interrupt, as well as the I 2 C master interrupt.Work aroundSeveral options are available:• When using 10-Bit Addressing mode, makecertain that the master and slave devices do notshare the same 2 MSbs of their addresses.If this cannot be avoided:• Clear the A10M bit (I2CxCON = 0) prior toperforming a Master mode transmit.• Read the ADD10 bit (I2CxSTAT) to checkfor a full 10-bit match whenever a slave I 2 Cinterrupt occurs on the master module.Affected Silicon RevisionsA3/A4B4 B5 B8X X X XA3/A4XB4 B5 B8EXAMPLE 1: CHECKING THE STATE OF SPIxIF AGAINST THE SPIx CLOCKwhile(IFS0bits.SPI1IF == 0){} //wait for the transmission to completewhile(PORTDbits.RD1 == 1){} //wait for the last clock to finishSPI1BUF = 0xFF;//write new data to the bufferDS80470G-page 14 2009-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY37. Module: I 2 C (Slave Mode)Under certain circumstances, a module operating inSlave mode may not respond correctly to some ofthe special addresses reserved by the I 2 C protocol.This happens when the following occurs:• 10-Bit Addressing mode is used (A10M = 1);and• bits, A, of the slave address(I2CADD) fall into the range of thereserved 7-bit address ranges: ‘1111xxx’ or‘0000xxx’.In these cases, the Slave module Acknowledgesthe command and triggers an I 2 C slave interrupt; itdoes not copy the data into the I2CxRCV registeror set the RBF bit.Work aroundDo not set bits, A, of the module’s slaveaddress equal to ‘1111xxx’ or ‘0000xxx’.Affected Silicon RevisionsA3/A4B4 B5 B8X X X X38. Module: I 2 CThe Transmit Buffer Full flag, TBF (I2CxSTAT),may not be cleared by hardware if a collision onthe I 2 C bus occurs before the first falling clockedge during a transmission.Work aroundNone.Affected Silicon RevisionsA3/A4XB4 B5 B839. Module: UARTWhen the UART is operating using two Stop bits(STSEL = 1), it may sample the first Stop bitinstead of the second one. If the device beingcommunicated with is one using one Stop bit in itscommunications, this may lead to framing errors.Work aroundNone.Affected Silicon RevisionsA3/A4B4 B5 B8X X X X40. Module: Oscillator (SOSC)The Low-Power Secondary Oscillator (SOSC)option, selected by the SOSCSEL Configurationbits (CW2), is not available in this siliconrevision. The oscillator in all devices functions in theDefault (High-Gain) mode only.Work aroundNone.Affected Silicon RevisionsA3/A4X41. Module: Voltage RegulatorThe Standby mode wake-up option, selected bythe WUTSEL Configuration bits (CW2), isnot available in this silicon revision. All devices usethe default regulator wake-up time of 190 s.Work aroundNone.B4 B5 B8Affected Silicon RevisionsA3/A4XB4 B5 B8 2009-2013 Microchip Technology Inc. DS80470G-page 15
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Page 5 and 6: PIC24FJ64GA004 FAMILYSilicon Errata
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PIC24FJ64GA004 Family Silicon Errata and Data Sheet ... - Microchip

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