PIC24FJ64GA004 Family Silicon Errata and Data Sheet ... - Microchip

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PIC24FJ64GA004 FAMILYTABLE 2:ModuleSILICON ISSUE SUMMARYFeatureItemNumberIssue SummaryJTAG — 1. Persistent pull-up (RA3) when JTAGXdisabled.LVD — 2. No LVD interrupt with low-voltage condition Xat Reset.Core Idle mode 3. Clock failure trap fails in Idle mode. XCore Doze mode 4. RAM read repeats on entering Doze mode. XCore BOR 5. POR and BOR flags both set on BOR. XCore RAM 6. RAM size implementation on some devices. XA/D — 7. Unimplemented channels may be selected. XA/D — 8. Missing midscale conversion code. XA/D — 9. Device may not wake when convert on INT0 Xtrigger is selected.I 2 C SDA Line 10. Line state may not be detected correctly. XState (I2C1)UART — 11. Reception failures in High-Speed mode. XUART — 12. Erroneous baud rate calculations inXHigh-Speed mode.UART Auto-Baud 13. Double receive interrupt with auto-baud Xreception.UART Auto-Baud 14. Insertion of spurious data with auto-baud Xreception.UART Auto-Baud 15. Auto-baud calculation errors causingtransmit or receive failures.XUARTOutputCompareSPIBreakCharacterGeneration16. The UART module will not generateback-to-back Break characters.— 17. Single missed compare events under certainconditions.EnhancedBuffer mode18. Some flag bits are set at incorrect times inEnhanced Buffer mode.SPI — 19. Module in Slave mode may ignore SSx pinand receive data anyway.SPIEnhancedBuffer mode20. No SPIx interrupt in Enhanced Buffer modeunder certain conditions.I/O — 21. Spec change for VOL and VOH. XI/O — 22. OSCO/RA3 driven immediately following XPOR.JTAG — 23. Sync loss in ICSP mode. XNote 1: Only those issues indicated in the last column apply to the current silicon revision.Affected Revisions (1)A3/A4 B4 B5 B8X X X XXXXXDS80470G-page 2 2009-2013 Microchip Technology Inc.
PIC24FJ64GA004 FAMILYTABLE 2:RTCC — 24. Write errors to ALCFGRPT register. XI 2 C Slave mode 25. In Slave mode, ACKSTAT bit state change. XI 2 C — 26. Issues with write operations on I2CxSTAT. XUART IrDA ® 27. IR baud clock only available during transmit. XI/O PPS 28. Issues with digital signal priorities with RP12 Xand RP18.UART UERIF 29. No UERIF flag with multiple errors. X X X XInterruptUART FIFO Error 30. PERR and FERR are not correctly set for all X X X XFlagsbytes in receive FIFO.Core BOR 31. Spontaneous BOR events with low-rangeVDD.X X X XCoreInstructionSet32. Loop count errors with REPEAT instructionand R-A-W stalls.Memory PSV 33. False address error traps at lower boundaryof PSV space.RTCC — 34. Decrement of alarm repeat counter undercertain conditions.SPIModuleI 2 CSILICON ISSUE SUMMARY (CONTINUED)MastermodeMastermode35. SPIF and SPIBEN may become set earlyunder certain conditions.36. Module may respond to its own mastertransmission as a slave under certainconditions.XX X XX X XXX X X XI 2 C Slave mode 37. Failure to respond correctly to someX X X Xreserved addresses in 10-bit mode.I 2 C — 38. TBF flag not cleared under certainXconditions.UART — 39. Erroneous sampling and framing errors X X X Xwhen using two Stop bits.Oscillator SOSC 40. Low-power SOSC unimplemented. XVoltage — 41. Standby mode not available. XRegulatorCore Code-Protect 42. General code protection disablesXbootloader functionality.SPIx — 43. Interrupts when SPIx is operating inX X X XEnhanced Buffer mode.UART IrDA ® 44. RXINV bit operation is inverted in IrDA ® XmodeCore Doze Mode 45. Instruction execution glitches followingDOZE bit changes.X X X XNote 1:FeatureItemNumberIssue SummaryOnly those issues indicated in the last column apply to the current silicon revision.Affected Revisions (1)A3/A4 B4 B5 B8 2009-2013 Microchip Technology Inc. DS80470G-page 3
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