PCI Express Base Specification v1.0 - 2002.pdf

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PCI EXPRESS BASE SPECIFICATION, REV 1.0FIGURE 3-12: TLP WITH LCRC AND SEQUENCE NUMBER APPLIED............................... 130FIGURE 3-13: TLP FOLLOWING APPLICATION OF SEQUENCE NUMBER AND RESERVED BITS................................................................................................................................. 132FIGURE 3-14: CALCULATION OF LCRC........................................................................... 134FIGURE 3-15: RECEIVED DLLP ERROR CHECK FLOWCHART.......................................... 139FIGURE 3-16: ACK/NAK DLLP PROCESSING FLOWCHART ............................................. 140FIGURE 3-17: RECEIVE DATA LINK LAYER HANDLING OF TLPS .................................... 145FIGURE 4-1: HIGH LEVEL LAYERING DIAGRAM HIGHLIGHTING PHYSICAL LAYER......... 149FIGURE 4-2: CHARACTER TO SYMBOL MAPPING............................................................. 150FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1 EXAMPLE................ 151FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4 EXAMPLE................ 151FIGURE 4-5: TLP WITH FRAMING SYMBOLS APPLIED..................................................... 154FIGURE 4-6: DLLP WITH FRAMING SYMBOLS APPLIED .................................................. 155FIGURE 4-7: FRAMED TLP ONAX1LINK ....................................................................... 155FIGURE 4-8: FRAMED TLP ONAX2LINK ....................................................................... 156FIGURE 4-9: FRAMED TLP ONAX4LINK ....................................................................... 156FIGURE 4-10: LFSR WITH SCRAMBLING POLYNOMIAL................................................... 157FIGURE 4-11: WIDTH NEGOTIATION, SIMPLIFIED STATE MACHINE, DOWNSTREAMCOMPONENT (PART 1).............................................................................................. 170FIGURE 4-12: WIDTH NEGOTIATION, SIMPLIFIED STATE MACHINE, DOWNSTREAMCOMPONENT (PART 2).............................................................................................. 171FIGURE 4-13: WIDTH NEGOTIATION, SIMPLIFIED STATE MACHINE, UPSTREAMCOMPONENT (PART 1).............................................................................................. 172FIGURE 4-14: WIDTH NEGOTIATION, SIMPLIFIED STATE MACHINE, UPSTREAMCOMPONENT (PART 2).............................................................................................. 173FIGURE 4-15: WIDTH NEGOTIATION EXAMPLE ............................................................... 174FIGURE 4-16: LINK WIDTH NEGOTIATION; STEPS 1,2..................................................... 176FIGURE 4-17: LINK WIDTH NEGOTIATION; STEPS 3, 4.................................................... 177FIGURE 4-18: LINK WIDTH NEGOTIATION; STEPS 5, 6.................................................... 179FIGURE 4-19: MAIN STATE DIAGRAM FOR LINK TRAINING AND STATUS STATE MACHINE................................................................................................................................. 183FIGURE 4-20: DETECT SUB-STATE MACHINE.................................................................. 184FIGURE 4-21: POLLING SUB-STATE MACHINE ................................................................ 186FIGURE 4-22: CONFIGURATION SUB-STATE MACHINE.................................................... 188FIGURE 4-23: RECOVERY SUB-STATE MACHINE.............................................................. 189FIGURE 4-24: L0S SUB-STATE MACHINE ......................................................................... 191FIGURE 4-25: L1 SUB-STATE MACHINE........................................................................... 192FIGURE 4-26: L2 SUB-STATE MACHINE.......................................................................... 193FIGURE 4-27: LOOPBACK STATE MACHINE..................................................................... 195FIGURE 4-28: SAMPLE DIFFERENTIAL SIGNAL ................................................................. 202FIGURE 4-29: SAMPLE TRANSMITTED WAVEFORM SHOWING -3.5 DB DE-EMPHASISAROUND A 0.5 V COMMON MODE........................................................................... 203FIGURE 4-30: A 30 KHZ BEACON SIGNALING THROUGH A 75 NFCAPACITOR............. 205FIGURE 4-31: BEACON, WHICH INCLUDES A 2 NS PULSE THROUGH A 75 NFCAPACITOR................................................................................................................................. 20510
PCI EXPRESS BASE SPECIFICATION, REV 1.0FIGURE 4-32: MINIMUM TRANSMITTER TIMING AND VOLTAGE OUTPUT COMPLIANCESPECIFICATION......................................................................................................... 209FIGURE 4-33: COMPLIANCE TEST/MEASUREMENT LOAD................................................ 210FIGURE 4-34: MINIMUM RECEIVER EYE TIMING AND VOLTAGE COMPLIANCESPECIFICATION......................................................................................................... 214FIGURE 5-1: PCI EXPRESS ROOT COMPLEX DEVICE MAPPING ....................................... 216FIGURE 5-2: PCI EXPRESS SWITCH DEVICE MAPPING ................................................... 216FIGURE 5-3: PCI EXPRESS CONFIGURATION SPACE LAYOUT.......................................... 217FIGURE 5-4: COMMON CONFIGURATION SPACE HEADER................................................ 223FIGURE 5-5: TYPE 0CONFIGURATION SPACE HEADER.................................................... 228FIGURE 5-6: TYPE 1CONFIGURATION SPACE HEADER.................................................... 229FIGURE 5-7: PCI POWER MANAGEMENT CAPABILITY STRUCTURE................................. 232FIGURE 5-8: POWER MANAGEMENT CAPABILITIES ......................................................... 232FIGURE 5-9: POWER MANAGEMENT STATUS/CONTROL.................................................. 233FIGURE 5-10: PCI EXPRESS CAPABILITY STRUCTURE..................................................... 234FIGURE 5-11: PCI EXPRESS CAPABILITY LIST REGISTER................................................ 235FIGURE 5-12: PCI EXPRESS CAPABILITIES REGISTER ..................................................... 235FIGURE 5-13: DEVICE CAPABILITIES REGISTER .............................................................. 237FIGURE 5-14: DEVICE CONTROL REGISTER..................................................................... 241FIGURE 5-15: DEVICE STATUS REGISTER........................................................................ 244FIGURE 5-16: LINK CAPABILITIES REGISTER................................................................... 246FIGURE 5-17: LINK CONTROL REGISTER......................................................................... 248FIGURE 5-18: LINK STATUS REGISTER............................................................................ 250FIGURE 5-19: SLOT CAPABILITIES REGISTER .................................................................. 251FIGURE 5-20: SLOT CONTROL REGISTER......................................................................... 253FIGURE 5-21: SLOT STATUS REGISTER............................................................................ 255FIGURE 5-22: ROOT CONTROL REGISTER........................................................................ 256FIGURE 5-23: ROOT STATUS REGISTER........................................................................... 257FIGURE 5-24: PCI EXPRESS EXTENDED CONFIGURATION SPACE LAYOUT ..................... 258FIGURE 5-25: PCI EXPRESS ENHANCED CAPABILITY HEADER ....................................... 259FIGURE 5-26: PCI EXPRESS ADVANCED ERROR REPORTING EXTENDED CAPABILITYSTRUCTURE.............................................................................................................. 260FIGURE 5-27: ADVANCED ERROR REPORTING ENHANCED CAPABILITY HEADER ........... 261FIGURE 5-28: UNCORRECTABLE ERROR STATUS REGISTER ............................................ 262FIGURE 5-29: UNCORRECTABLE ERROR MASK REGISTER............................................... 263FIGURE 5-30: UNCORRECTABLE ERROR SEVERITY REGISTER......................................... 264FIGURE 5-31: CORRECTABLE ERROR STATUS REGISTER................................................. 265FIGURE 5-32: CORRECTABLE ERROR MASK REGISTER ................................................... 265FIGURE 5-33: ADVANCED ERROR CAPABILITIES AND CONTROL REGISTER .................... 266FIGURE 5-34: HEADER LOG REGISTER............................................................................ 267FIGURE 5-35: ROOT ERROR COMMAND REGISTER.......................................................... 268FIGURE 5-36: ROOT ERROR STATUS REGISTER............................................................... 269FIGURE 5-37: ERROR SOURCE IDENTIFICATION REGISTER.............................................. 270FIGURE 5-38: PCI EXPRESS VIRTUAL CHANNEL CAPABILITY STRUCTURE..................... 271FIGURE 5-39: VIRTUAL CHANNEL ENHANCED CAPABILITY HEADER.............................. 272FIGURE 5-40: PORT VC CAPABILITY REGISTER 1 ........................................................... 27311
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