PCI Express Base Specification v1.0 - 2002.pdf

PCI EXPRESS BASE SPECIFICATION, REV. 1.0UpstreamComponentStateD0D0D0D0LinkStateL1L1L0L0DownstreamComponentStateD1D1D0 D1D0StandbyStatePM ConfigurationRequest triggersL1 to L0 TransitionL1 to L0TransitionCompletePM ConfigurationRequestDeliveredFigure 6-3: Exit from L1 Link State Initiated by Upstream ComponentSequence of events:1. Power management software initiates a configuration cycle targeting a PMconfiguration register (the PowerState field of the PMCSR in this example) within afunction that resides in the Downstream component (e.g., to bring the function backto the D0 state).2. The Upstream component detects that a configuration cycle is intended for a Linkthat is currently in a low power state, and as a result, initiates a transition of that Linkinto the L0 state.3. In accordance with the Chapter 4 definition, both directions of the Link enter intoLink training, resulting in the transition of the Link to the L0 state. The L1 L0transition is discussed in detail in Chapter 4.4. Once both directions of the Link are back to the active L0 state, the Upstream Portsends the configuration Packet Downstream.6.3.2.3. Entry into the L2/L3 Ready StateTransition to the L2/L3 Ready state follows a process that is similar to the L1 entry process.There are some minor differences between the two that are spelled out below.• L2/L3 Ready entry transition protocol does not immediately result in an L2 or L3Link state. The transition to L2/L3 Ready is effectively a handshake to establish thedownstream component’s readiness for power removal. L2 or L3 is ultimatelyachieved when the platform removes the components’ power and reference clock.306