PCI Express Base Specification v1.0 - 2002.pdf

PCI EXPRESS BASE SPECIFICATION, REV 1.0TABLE 5-11: DEVICE CAPABILITIES REGISTER................................................................ 237TABLE 5-12: DEVICE CONTROL REGISTER...................................................................... 241TABLE 5-13: DEVICE STATUS REGISTER......................................................................... 245TABLE 5-14: LINK CAPABILITIES REGISTER.................................................................... 246TABLE 5-15: LINK CONTROL REGISTER .......................................................................... 248TABLE 5-16: LINK STATUS REGISTER ............................................................................. 250TABLE 5-17: SLOT CAPABILITIES REGISTER ................................................................... 251TABLE 5-18: SLOT CONTROL REGISTER.......................................................................... 253TABLE 5-19: SLOT STATUS REGISTER............................................................................. 255TABLE 5-20: ROOT CONTROL REGISTER......................................................................... 257TABLE 5-21: ROOT STATUS REGISTER ............................................................................ 258TABLE 5-22: PCI EXPRESS ENHANCED CAPABILITY HEADER ........................................ 259TABLE 5-23: ADVANCED ERROR REPORTING ENHANCED CAPABILITY HEADER ............ 261TABLE 5-24: UNCORRECTABLE ERROR STATUS REGISTER ............................................. 262TABLE 5-25: UNCORRECTABLE ERROR MASK REGISTER................................................ 263TABLE 5-26: UNCORRECTABLE ERROR SEVERITY REGISTER.......................................... 264TABLE 5-27: CORRECTABLE ERROR STATUS REGISTER.................................................. 265TABLE 5-28: CORRECTABLE ERROR MASK REGISTER .................................................... 266TABLE 5-29: ADVANCED ERROR CAPABILITIES REGISTER.............................................. 266TABLE 5-30: HEADER LOG REGISTER ............................................................................. 267TABLE 5-31: ROOT ERROR COMMAND REGISTER ........................................................... 268TABLE 5-32: ROOT ERROR STATUS REGISTER ................................................................ 269TABLE 5-33: ERROR SOURCE IDENTIFICATION REGISTER ............................................... 270TABLE 5-34: VIRTUAL CHANNEL ENHANCED CAPABILITY HEADER............................... 272TABLE 5-35: PORT VC CAPABILITY REGISTER 1 ............................................................ 273TABLE 5-36: PORT VC CAPABILITY REGISTER 2............................................................. 275TABLE 5-37: PORT VC CONTROL REGISTER ................................................................... 276TABLE 5-38: PORT VC STATUS REGISTER ...................................................................... 277TABLE 5-39: VC RESOURCE CAPABILITY REGISTER....................................................... 278TABLE 5-40: VC RESOURCE CONTROL REGISTER .......................................................... 279TABLE 5-41: VC RESOURCE STATUS REGISTER ............................................................. 282TABLE 5-42: DEFINITION OF THE 4-BIT ENTRIES IN THE VC ARBITRATION TABLE ......... 283TABLE 5-43 LENGTH OF THE VC ARBITRATION TABLE................................................... 283TABLE 5-44: LENGTH OF PORT ARBITRATION TABLE ..................................................... 284TABLE 5-45: DEVICE SERIAL NUMBER ENHANCED CAPABILITY HEADER ...................... 285TABLE 5-46: SERIAL NUMBER REGISTER........................................................................ 286TABLE 5-47: POWER BUDGETING ENHANCED CAPABILITY HEADER .............................. 288TABLE 5-48: POWER BUDGETING DATA REGISTER......................................................... 289TABLE 5-49: POWER BUDGET CAPABILITY REGISTER .................................................... 291TABLE 6-1: SUMMARY OF PCI EXPRESS LINK POWER MANAGEMENT STATES............... 298TABLE 6-2: RELATION BETWEEN POWER MANAGEMENT STATES OF LINK ANDCOMPONENTS........................................................................................................... 302TABLE 6-3: ENCODING OF THE ACTIVE STATE LINK PM SUPPORT FIELD....................... 327TABLE 6-4: DESCRIPTION OF THE SLOT CLOCK CONFIGURATION FIELD ......................... 327TABLE 6-5: DESCRIPTION OF THE COMMON CLOCK CONFIGURATION FIELD .................. 328TABLE 6-6: ENCODING OF THE L0S EXIT LATENCY FIELD .............................................. 32814