PCI Express Base Specification v1.0 - 2002.pdf

PCI EXPRESS BASE SPECIFICATION, REV. 1.0A.9.Considerations for Bandwidth AllocationA.9.1. Isochronous Bandwidth of PCI Express LinksIsochronous bandwidth budgeting for PCI Express Links can be derived based on Linkparameters such as isochronous payload size, the speed, and the width of the Link.Isochronous bandwidth allocation for a PCI Express Link is limited to certain percentage ofthe maximum effective Link bandwidth in order to leave sufficient bandwidth for nonisochronoustraffic and to account for temporary Link bandwidth reduction due to retries.Link utilization is counted based on the actual cycles consumed on the physical PCI ExpressLink. The maximum number of virtual timeslots allowed per Link (N link ) depends on theisochronous packet payload size and also the speed and width of the Link. Table A-2: showsN link and Link utilization as functions of isochronous payload size and PCI Express Linkwidth when the Link runs at 2.5 GHz and isochronous Link utilization limited to 50%. Forlow to medium PCI Express Links width (with number of Lanes between 1 and 8), therelatively slow Link bandwidth limits the isochronous resource (virtual timeslot) allocation.However, for wider PCI Express Links (with 12 or 16 Lanes), the relatively large virtualtimeslot (at 100 n) limits the isochronous resource allocation.Table A-2: Maximum Number of Virtual Timeslots Allowed for Different PCIExpress Links at 2.5 GHz# Lanes 1 2 48 12 16Y (Bytes) N link %Util N link %Util N link %Util N link %Util N link %Util N link %Util128 11 50% 22 50% 44 50% 88 50% 128 48% 128 36%256 5 43% 11 47% 23 49% 46 49% 70 50% 93 50%512 3 50% 6 50% 12 50% 24 50% 36 50% 48 50%As isochronous bandwidth allocation on a PCI Express Link is based on number oftransactions N link per isochronous period. There is no distinction between read requests andwrite requests in budgeting isochronous bandwidth on a PCI Express Link. In other words,even though a read request packet (without payload) can be much smaller than a writerequest packet (with payload), their Link utilization is accounted as the same according to thelarger one (a write request). This is because for each read request in one direction of a PCIExpress Link there will be one or more read completions with payload on the otherdirection of the PCI Express Link. Without differentiating between read and write requesttransactions, the allocated isochronous bandwidth for a PCI Express Link in the Endpointto-Root-Complexmodel is assumed to consume bandwidth in both directions. For thepush-only Peer-to-Peer model, software may take advantage of the unidirectionalisochronous traffic pattern in budgeting PCI Express Link resource.393