PCI Express Base Specification v1.0 - 2002.pdf

PCI EXPRESS BASE SPECIFICATION, REV. 1.0Table 2-14: Error MessagesError MessageERR_CORERR_NONFATALERR_FATALDescriptionThis Message is issued when the component or device detects acorrectable error on the PCI Express interface. The RootComplex is the ultimate recipient for this Message.This Message is issued when the component or device detects anon-fatal, uncorrectable error on the PCI Express interface. TheRoot Complex is the ultimate recipient for this Message.This Message is issued when the component or device detects afatal, uncorrectable error on the PCI Express interface. The RootComplex is the ultimate recipient for this Message.The initiator of the message is identified with the Requester ID of the message header. TheRoot Complex translates these error messages into platform level events. Refer toSection 7.2 for details on uses for these messages.2.8.1.4. Messages for Support of Locked TransactionsThe PCI Express specification defines the Unlock Message to support Lock Transactionsequences. The following rules apply to Unlock Message:• The Unlock Message must use the default Traffic Class designator (TC0)See Section 7.5 for details on implementing support for Lock Transaction sequences.2.8.1.5. Slot Power Limit SupportThe Set_Slot_Power_Limit message includes a one DW data payload. This message is usedto convey a slot power limitation value from a Downstream Port (of a Root Complex or aSwitch) to an Upstream Port of component (Endpoint, Switch or a PCI Express-PCIBridge) attached to the same Link. The data payload is copied from the Slot CapabilitiesRegister of the Downstream Port and is written into the Device Capabilities Register of theUpstream Port on the other side of the Link. Bits 9:8 of the data payload map to the SlotPower Limit Scale field and Bits 7:0 map to the Slot Power Limit Value field. This message issent automatically by the Downstream Port (of a Root Complex or a Switch) when one ofthe following events occurs:o On a Configuration Write to the Slot Capabilities Register (see Section 5.8.9) when theData Link Layer reports DL_Up status.o Anytime when Link transitions from a non-DL_Up status to a DL_Up status (seeSection 2.14).The component on the other side of the Link (Endpoint, Switch or PCI Express-PCIBridge) that receives Set_Slot_Power_Limit message must copy the values in the datapayload into the Device Capabilities Register associated with the component’s UpstreamPort. PCI Express components that are targeted exclusively for integration on the systemplanar (e.g. motherboard) as well as components that are targeted for integration on acard/module where power consumption of the entire card/module is below the lowest94