PCI Express Base Specification v1.0 - 2002.pdf

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<strong>PCI</strong> EXPRESS BASE SPECIFICATION, REV. 1.0Link ConfigurationSteps 1, 2Upstream CompDownstream Port(s)Downstream CompUpstream PortEntryEntryStep 1Config.RcvCfgStep 1TS1TS1Config.RcvCfgStep 2TS1Config.RcvCfgStep 2Config.RcvCfgStep 3Figure 4-16: Link Width Negotiation; Steps 1,2In order to enter the configuration state, Lanes within a perspective Link have alreadyexchanged TS1 ordered-sets and completed the bit synchronization, polarity inversion (ifneeded) and symbol synchronization functions. Prior to entering the configuration state, theLink number and Lane number fields have been set to PAD (K23.7) and TS1 ordered-setsare sent repeatedly.Step 1:Upon entering Config.RcvrCfg, the downstream port(s) starts the Link width and Laneordering negotiations by sending out the TS1 ordered-set with a unique Link number onsets of Lanes, which that component could support as unique links; the Lane numberscontinue to be set to PAD.Step 2:Upon receipt of the TS1 ordered-set with Link numbers (non-PADs) present in the Linknumber field, the upstream port shall respond by choosing one of the Link numbers itreceived. This step of returning the one Link number determines the downstreamport(s) the number of links that are to be negotiated.The upstream port responds with a Link number only on the Lanes in which it receiveda Link number and Lanes that it can support in one Link. A simple example: a port may176
<strong>PCI</strong> EXPRESS BASE SPECIFICATION, REV. 1.0be designed to support a x32 Link. Only 16 of those Lanes may have been attached, andtherefore TS1s received only on 16 Lanes. The port may not support a x16 Link, butmay support a x12 Link. In that case, the upstream port returns TS1 ordered-sets with aLink number only on the 12 Lanes that it is capable of supporting in a x12, and with theLink number set to PAD on the 4 remaining Lanes. This is the first counter-proposaltowards establishing the final Link width.Additional notes on steps 1 and 2:One method to create a cross-link Section 1.6 is to connect a downstream port toanother downstream port. One of two scenarios can occur; a.) The two ports choosedifferent Link numbers to begin negotiations, or b.) The two ports choose the same Linknumber to begin negotiation. If a.) occurs, the rules are described as part of step 3. Ifb.) occurs, the two ports will not yet be able to differentiate the Step 1 behavior of across-link condition from the Step 2 behavior of a normal upstream port.Note: If a system designer connects two (or more) downstream ports on one upstreamcomponent that is capable of being aggregated into one Link (Link aggregation) in across-link to two downstream ports on a different upstream component, theconfiguration results are undefined.ConfigurationSteps 3, 4Upstream CompDownstream Port(s)Return to Step 2SeeNote4Downstream CompUpstream PortEntry From Step 2Step 3Config.RcvCfgStep 3TS1See Note 1Step 4TS1See Note 2TS1See Note 3Config.RcvCfgStep 4Config.WaitStep 5Figure 4-17: Link Width Negotiation; Steps 3, 4Steps 3 and 4 establish Lane ordering within each Link established in Steps 1 and 2. To finda supported Link width common to both components, Steps 3 and 4 continue to reduce theLink width by removing select Lanes from the negotiation; Lanes never join a Linknegotiation through these steps. Returning a Lane’s Link number to the value of PADindicates removal; otherwise Link numbers persist with the value assigned in Step 2.177
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PCI Express Base Specification v1.0 - 2002.pdf

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