PCI Express Base Specification v1.0 - 2002.pdf

PCI EXPRESS BASE SPECIFICATION, REV. 1.0The Transaction Layer comprehends the following:• TLP construction and processing• Association of PCI Express transaction-level mechanisms with device resourcesincluding:o Flow Controlo Virtual Channel management• Rules for ordering and management of TLPso Including Traffic Class differentiationThis chapter specifies the behaviors associated with the Transaction Layer.2.2. Address Spaces, Transaction Types, and UsageTransactions form the basis for information transfer between a Requester and Completer.Four address spaces are defined within the PCI Express architecture, and differentTransaction types are defined, each with its own unique intended usage, within each addressspace as shown in Table 2-1.Table 2-1: Transaction Types for Different Address SpacesAddress Space Transaction Types Basic UsageMemoryReadWriteTransfer data to/from a memory-mappedlocation.I/OReadWriteTransfer data to/from an I/O-mapped locationConfigurationMessageReadWriteBaselineVendor– definedAdvanced Switching2.2.1. Memory TransactionsMemory Transactions include the following types:• Read Request/Completion• Write RequestMemory Transactions use two different address formats:• Short Address Format: 32-bit address• Long Address Format: 64-bit addressDevice configuration/setupFrom event signaling mechanism to generalpurpose messaging44