PCI Express Base Specification v1.0 - 2002.pdf

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PCI EXPRESS BASE SPECIFICATION, REV 1.0A.2.4. Isochronous Transaction Latency ........................................................... 388A.2.5. An Example Illustrating Isochronous Parameters.................................. 389A.3. ISOCHRONOUS TRANSACTION RULES ............................................................... 390A.4. TRANSACTION ORDERING ................................................................................ 390A.5. ISOCHRONOUS DATA COHERENCY ................................................................... 390A.6. FLOW CONTROL ............................................................................................... 391A.7. TOPOLOGY RESTRICTIONS................................................................................ 391A.8. TRANSFER RELIABILITY ................................................................................... 392A.9. CONSIDERATIONS FOR BANDWIDTH ALLOCATION ........................................... 393A.9.1. Isochronous Bandwidth of PCI Express Links........................................ 393A.9.2. Isochronous Bandwidth of Endpoint Devices ......................................... 394A.9.3. Isochronous Bandwidth of Switches........................................................ 394A.9.4. Isochronous Bandwidth of Root Complex............................................... 394A.10. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS..................................... 394A.10.1. A PCI Express Endpoint Device as a Requester ..................................... 394A.10.2. A PCI Express Endpoint Device as a Completer .................................... 395A.10.3. Switches................................................................................................... 396A.10.4. Root Complex .......................................................................................... 397B. SYMBOL ENCODING ........................................................................................ 399C. PHYSICAL LAYER APPENDIX........................................................................ 409C.1. DATA SCRAMBLING ......................................................................................... 4098
PCI EXPRESS BASE SPECIFICATION, REV 1.0FiguresFIGURE 1-1: PCI EXPRESS LINK........................................................................................ 29FIGURE 1-2: EXAMPLE TOPOLOGY.................................................................................... 31FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ..................................................... 33FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ............................................................... 35FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ......................................................... 36FIGURE 1-6: ADVANCED PEER-TO-PEER COMMUNICATION .............................................. 41FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER.................. 43FIGURE 2-2: GENERIC TRANSACTION LAYER PACKET FORMAT........................................ 47FIGURE 2-3: TRANSACTION DESCRIPTOR .......................................................................... 48FIGURE 2-4: TRANSACTION ID.......................................................................................... 48FIGURE 2-5: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ...................................... 50FIGURE 2-6: VIRTUAL CHANNEL CONCEPT –AN ILLUSTRATION ...................................... 57FIGURE 2-7: VIRTUAL CHANNEL CONCEPT –SWITCH INTERNALS (UPSTREAM FLOW)..... 57FIGURE 2-8: AN EXAMPLE OF TC/VC CONFIGURATIONS.................................................. 60FIGURE 2-9: REQUEST HEADER FORMAT FOR 32B ADDRESSING OF MEMORY .................. 68FIGURE 2-10: REQUEST HEADER FORMAT FOR 64B ADDRESSING OF MEMORY................ 68FIGURE 2-11: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS.................................. 68FIGURE 2-12: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ............ 68FIGURE 2-13: REQUEST HEADER FORMAT FOR MSG REQUEST ......................................... 69FIGURE 2-14: REQUEST HEADER FORMAT FOR MSGDREQUEST ...................................... 69FIGURE 2-15: REQUEST HEADER FORMAT FOR MSGAS REQUEST.................................... 69FIGURE 2-16: REQUEST HEADER FORMAT FOR MSGASD REQUEST ................................. 69FIGURE 2-17: COMPLETION HEADER FORMAT .................................................................. 76FIGURE 2-18: COMPLETER ID ........................................................................................... 77FIGURE 2-19: FLOWCHART FOR HANDLING OF RECEIVED TLPS ....................................... 79FIGURE 2-20: FLOWCHART FOR SWITCH HANDLING OF TLPS........................................... 80FIGURE 2-21: FLOWCHART FOR HANDLING OF RECEIVED REQUEST ................................. 82FIGURE 2-22: INTX COLLAPSING IN A DUAL-HEADED BRIDGE ........................................ 92FIGURE 2-23: PAYLOAD_DEFINED MESSAGE.................................................................... 96FIGURE 2-24: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE COMPLETER ........... 99FIGURE 2-25: CALCULATION OF 32B ECRC FOR TLP END TO END DATA INTEGRITYPROTECTION............................................................................................................. 112FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK LAYER .................... 117FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE MACHINE...................... 119FIGURE 3-3: FLOWCHART DIAGRAM OF FLOW CONTROL INITIALIZATION PROTOCOL .... 122FIGURE 3-4: DLLP TYPE AND CRC FIELDS.................................................................... 126FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND NAK........................... 127FIGURE 3-6: DATA LINK LAYER PACKET FORMAT FOR INITFC1 .................................... 127FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR INITFC2 .................................... 127FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR UPDATEFC................................ 127FIGURE 3-9: PM DATA LINK LAYER PACKET FORMAT................................................... 127FIGURE 3-10: VENDOR SPECIFIC DATA LINK LAYER PACKET FORMAT .......................... 128FIGURE 3-11: DIAGRAM OF CRC CALCULATION FOR DLLPS......................................... 1299
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PCI Express Base Specification v1.0 - 2002.pdf

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