PCI Express Base Specification v1.0 - 2002.pdf

PCI EXPRESS BASE SPECIFICATION, REV. 1.0• Signaling rate – Once initialized, each Link must only operate at one of thesupported signaling levels. For this version of the specification, there is only onesignaling rate, which provides an effective 2.5 Gigabits/second/Lane/directionof raw bandwidth. The data rate is expected to increase with the technologyadvances in future.• Lanes – A Link must support at least one Lane – each Lane represents a set ofdifferential signal pairs (one pair for transmission, one pair for reception). Toscale bandwidth, a Link may aggregate multiple Lanes denoted by xN where Nmay be any of the supported Link widths. For example, an x8 Link represents anaggregate bandwidth of 20 Gigabits / second of raw bandwidth in each direction.This version of the Physical Layer supports x1, x2, x4, x8, x12, x16, and x32Lane widths.• Initialization - During hardware initialization, each PCI Express Link is set upfollowing a negotiation of Lane widths and frequency of operation by the twoagents at each end of the Link. No firmware or operating system software isinvolved.• Symmetry – Each Link must support a symmetric number of Lanes in eachdirection, i.e., an x16 Link indicates there are 16 differential signal pairs in eachdirection.1.3. PCI Express Fabric TopologyA fabric is composed of point-to-point Links that interconnect a set of components – anexample fabric topology is shown in Figure 1-2. This figure illustrates a single fabricinstance called a hierarchy – composed of a Root Complex (RC), multiple Endpoints (I/Odevices), a Switch, and PCI Express-PCI Bridge all interconnected via PCI Express Links.Each of the components of the topology are mapped in a single flat address space and canbe addressed by PCI-like load store accesses.30