PCI Express Base Specification v1.0 - 2002.pdf

PCI EXPRESS BASE SPECIFICATION, REV. 1.0Hierarchy DomainHost Bridgehot resetingressIngress PortI/O SpaceisochronousinvariantLaneLayerLinkLinkUpLogical Buslogical deviceLogical IdleMalformed PacketMemory SpaceMessageA PCI Express Hierarchy is segmented into multiple fragments by theRoot Complex that sources more than one PCI Express interface. Thesesub-hierarchies are called Hierarchy Domains.A Host Bridge is a part of a Root Complex which connects a host CPU orCPUs to a PCI Express Hierarchy.A reset propagated in-band across a Link using a Physical LayerMechanism.Refers to direction. Means incoming, i.e., receiving direction.Receiving port, i.e., the port that accepts incoming traffic. Typically usedas a reference to the role that port of the Switch has in the context of atransaction or more broadly in the context of traffic flow.One of the four address spaces of the PCI Express architecture.Identical to the I/O space defined in PCI.Refers to data associated with time-sensitive applications, such as audioor video applications.An invariant field of a TLP Header contains a value which cannot legallybe modified as the TLP flows through the PCI Express fabric.A set of differential signal pairs, one pair for transmission and one pairfor reception. A by-N Link is composed of N Lanes.Unit of distinction applied to the PCI Express Specification to clarify thebehavior of key elements of the interface. The use of the term Layer isnot intended to imply a specific implementation.A dual-simplex communications path between two components. Thecollection of two Ports and their interconnecting Lanes.Status from the Physical layer to the Link layer indicating both ends ofthe Link are connected.The logical connection among a collection of devices that have the samebus number in Configuration Space.An element of a PCI Express system that responds to a unique devicenumber in Configuration Space. As for physical devices in PCI 2.3,logical devices either include a single function or are multi-functiondevices. Furthermore, the term “logical device” is often used whendescribing requirements that apply individually to all functions within thelogical device. Unless otherwise specified, logical device requirementsin this specification apply to single function logical devices and to eachfunction individually of a multi-function logical device.A period of one or more symbol times when no information: TLPs,DLLPs, or any special symbol is being transmitted or received. Unlikeelectrical idle, during logical idle the idle character is being transmittedand received.A TLP which violates TLP formation rules.One of the four address spaces of the PCI Express architecture.Identical to the memory space defined in PCI.A Packet with a Message Space type.22