PCI Express Base Specification v1.0 - 2002.pdf

PCI EXPRESS BASE SPECIFICATION, REV. 1.0• When the Time-based WRR Port Arbitration is used for a VC of any given port, a phasecontaining that port's Port Number indicates an 'idle' time-slot for the Port Arbiter.The table entry size is determined by the Port Arbitration Table Entry Size field in the VCResource Capability Register 1. The length of the table is determined by the Port ArbitrationSelect field as shown in Table 5-44.When the Port Arbitration Table is used by the default Port Arbitration for the default VC,the default values for the table entries must contain at least one entry for each of other PCIExpress ports of the device to ensure forward progress for the default VC for each port. Thetable may contain RR or RR-like fair Port Arbitration for the default VC.31 30 5 4 3 2 1 0 Byte LocationPhase[15] … … … … … Phase[1] Phase[0] 00hPhase[31] … … … … … Phase[17] Phase[16] 04h08h0Ch10h14hPhase[111] … … … … … Phase[97] Phase[96] 18hPhase[127] … … … … … Phase[113] Phase[112] 1ChFigure 5-48: Example Port Arbitration Table with 128 Phases and 2-bit Table EntriesTable 5-44: Length of Port Arbitration TablePort Arbitration SelectPort Arbitration Table Length (in # of Entries)001b 32010b 64011b 128100b 128284