Buffering in the Layout Environment - Computer Engineering ...

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s1s2s1s2Figure 28.11: A graph for generating optimal subtree.general. Therefore, a general problem is how to construct a buffered tree (or subtree) that drives acertain set of sinks Γ = {s 1 , s 2 , ...}. This is achieved by using an abstraction graph G Γ illustratedin Figure 28.11. This graph consists of a source node, which is the set of sinks Γ, and a set ofpossible buffer nodes. An edge (Γ, v) represents the optimal BC-subtree rooted at v, and its weightis the maximum delay of the BC-tree. The edge (u, v), where u, v ∉ Γ, represents the optimalbuffered path between u and v which can be found in the look-up table. Then, the shortest pathfrom Γ to each other node v corresponds to the optimal subtree connecting to the sink set Γ. Thealgorithm proceeds to creates subtrees by increasingly considering more sinks.This algorithm can minimize the maximum source-sink delay, but not the timing slack. In fact,it can reach the optimal solution in exponential time.5 Layout Environment Aware Buffered Steiner TreeThe previous sections present different algorithms buffer insertion and buffered tree constructionavoiding buffer placement blockages. Practically, it is essential that buffer insertion algorithmsconsider layout environment such as the placement and routing congestion, which obviously leadsto a more complicated problem. In this section, we start with the congestion assessment and thenintroduce several related algorithms.12
g ig jFigure 28.12: An example of tile graph.5.1 Measurement of Placement and Routing CongestionIn order to evaluate the placement and routing congestion of a buffered net, a tile graph is usuallyused to capture the congestion information and at the same time reduce the problem complexity.The tile graph is represented as G = (V G , E G ) such that V G = {g 1 , g 2 , ...} is a set of tiles and E Gis a set of boundaries each (g i , g j ) of which is between two adjacent tiles g i and g j . An example ofthe tile graph is shown in Figure 28.12. If a tile g i ∈ V G has an area of A(g i ) and its area occupiedby placed cells are a(g i ), the placement density is defined as d(g i ) = a(g i)A(g i ) . Let W(g i, g j ) be themaximum number of wire tracks that can be routed across the tile boundary (g i , g j ) and w(g i , g j ) bethe number of used tracks crossing (g i , g j ). Similarly, the boundary density is d(g i , g j ) = w(g i,g j )W(g i ,g j ) .In order to increase the penalty of using a congested tile (similarly for a tile boundary), usingsquare cost (i.e., d(g i ) 2 ) ensure the cost increases more rapidly as a tile is closer to becoming full.For example, the cost of using two tiles with densities of 0.1 and 0.9 is 0.82, while the cost of usingtwo tiles with densities of 0.5 is 0.5. When considering both the placement and routing congestioncost for a net, the total cost incurred can be a linear expression of squares of both the tile densitiesand boundary densities.13
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