Buffering in the Layout Environment - Computer Engineering ...

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candidates, which is chosen by the user to obtain the desired timing performance/CPU trade-off.For example, Figure 28.15(a) has a value of that is twice that of Figure 28.15(b). For asymmetricspacing, a penalty is associated for spacing tiles either closer to or further from the desired spacingS. We define a function pen(x, S, L) = (x−S)2(L−S) 2 that assigns a penalty cost on an edge when thedistance x between tiles is not equal to S. Together with the congestion consideration, the totalcost of a path is the summation over the penalty cost of all edges and the congestion cost of all tileson the path. Hence, the problem can be solved by a topological sort, which finds the minimum costpath from the source to all sinks. By apply this pre-processing technique, buffers finally insertedsignificantly improve the overall design congestion with virtually no impact on either computationtime or buffered net delays. In fact, since the pre-processing is more selective of the potentialbuffer insertion candidates, the final buffer insertion process can be speed up dramatically.22
References[1] H. Zhou, D. F. Wong, I-M. Liu, and A. Aziz. Simultaneous routing and buffer insertion withrestrictions on buffer locations. IEEE Transactions on Computer-Aided Design, 19(7):819–824, July 2000. (ICCD 2001).[2] S.-W. Hur, A. Jagannathan, and J. Lillis. Timing driven maze routing. In Proceedings of theACM International Symposium on Physical Design, pages 208–213, 1999.[3] A. Jagannathan, S.-W. Hur, and J. Lillis. A fast algorithm for context-aware buffer insertion.In Proceedings of the ACM/IEEE Design Automation Conference, pages 368–373, 2000.[4] M. Lai and D. F. Wong. Maze routing with buffer insertion and wiresizing. In Proceedingsof the ACM/IEEE Design Automation Conference, pages 374–378, 2000.[5] C. J. Alpert, G. Gandham, J. Hu, J. L. Neves, S. T. Quay, and S. S. Sapatnekar. A Steinertree construction for buffers, blockages, and bays. IEEE Transactions on Computer-AidedDesign, 20(4):556–562, April 2001.[6] J. Hu, C. J. Alpert, S. T. Quay, and G. Gandham. Buffer insertion with adaptive blockageavoidance. IEEE Transactions on Computer-Aided Design, 22(4):492–498, April 2003.[7] L. P. P. P. van Ginneken. Buffer placement in distributed RC-tree networks for minimalElmore delay. In Proceedings of the IEEE International Symposium on Circuits and Systems,pages 865–868, 1990.[8] J. Cong and X. Yuan. Routing tree construction under fixed buffer locations. In Proceedingsof the ACM/IEEE Design Automation Conference, pages 379–384, 2000.[9] X. Tang, R. Tian, H. Xiang, and D. F. Wong. A new algorithm for routing tree constructionwith buffer insertion and wire sizing under obstacle constraints. In Proceedings of theIEEE/ACM International Conference on Computer-Aided Design, pages 49–56, 2001.23
Page 4 and 5: ts(a)(b)Figure 28.3: Routing graph.
Page 6 and 7: uffer nodes. A buffer node always h
Page 8 and 9: 4.1 Tree Adjustment TechniqueAs a r
Page 10 and 11: the root of the subtree. The label
Page 12 and 13: s1s2s1s2Figure 28.11: A graph for g
Page 14 and 15: 5.2 Plate Based Tree AdjustmentWhen
Page 16 and 17: During the bottom-up process, each
Page 18 and 19: v1v1v5v6v2v4v3v4(a)(b)Figure 28.14:
Page 20 and 21: For Critical Nets, the cost impact
Page 24 and 25: [10] S. Dechu, Z. C. Shen, and C. C

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