Buffering in the Layout Environment - Computer Engineering ...

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5.2 Plate Based Tree AdjustmentWhen we consider both placement and routing congestions at the same time, applying simultaneousSteiner tree construction and buffer insertion seems to be computationally prohibitive forpractical circuit designs. In the following, sequential approaches [11, 12] are introduced to solvethe problems. A good way to handle the placement and routing congestion is through the followingfour stages: (1) Timing-driven Steiner tree construction; (2) Plate-based adjustment for congestionmitigation; (3) Local blockage avoidance (refer to Section 2.1); (4) Van Ginneken style buffer insertion.Since stages 1, 3 and 4 have been described in previous sections, the rest of the discussionfocuses on the stage of plate based tree adjustment.5.2.1 Dynamic Programming Based AdjustmentThe basic idea for the plate-based adjustment [13] is to perform a simplified simultaneous bufferinsertion and local tree adjustment so that the Steiner nodes and wiring paths can be moved to lesscongested regions without significant disturbance on the timing performance obtained in Stage1. The plate-based adjustment traverses the given Steiner topology in a bottom-up fashion bythe dynamic programming algorithm. During this process, Steiner nodes and wiring paths maybe adjusted together with buffer insertion to generate multiple candidate solutions. We only usebuffer insertion to estimate the placement congestion of the buffered tree and to guide the treeadjustment. Hence, the output of this stage is still an unbuffered net, only with changes in theSteiner tree routing. Besides, since buffer insertion is merely a mean of placement congestionestimation, a single “typical” buffer type can be used to simplify the calculation, while the Elmoredelay model can be used for interconnect and a switch level RC gate delay model is adopted.For a Steiner node v i which is located in a tile g k , a plate P(v i ) for v i is a set of tiles in theneighborhood of g k including g k itself. During the plate-based adjustment, we confine the locationchange for each Steiner node within its corresponding plate. If v i is a sink or the source node weset P(v i ) = {g k }. The shaded box in Figure 28.13(a) gives an example of the plate correspondingto Steiner node v 4 . The plate indicates any of the possible locations which the Steiner node may14
SourceSourcev1v5v1v5v1v5v4v3v4v3v4v3v2v2v2(a) (b) (c)Figure 28.13: (a) Candidate solutions are generated from v 2 and v 3 and propagated to every tile,which is shaded, in the plate for v 4 . Solution search is limited to the bounding boxes indicated bythe thickened dashed lines. (b) Solutions from v 1 and every tile in the plate for v 4 are propagatedto the plate for v 5 . (c) Solutions from plate of v 5 are propagated to the source and the thin solidlines indicate one of the alternative trees that may result from this process.be moved to.The search for alternative wiring paths is limited to the minimum bounding box covering theplates of two end nodes. In Figure 28.13, such bounding boxes are indicated by the thickeneddashed lines. Therefore, the size of plates define the search range for both Steiner nodes and wiringpaths. As a result, the size of the plate controls the quality of solution/runtime trade-off desired bythe user. With different plate size, we can obtain the ability to modify the topology to move Steinerpoints into low-congestion regions while also capping the runtime penalty. An example of how anew Steiner topology might be constructed from an existing topology is demonstrated in Figures28.13(a)-(c).It is suggested in [14] that buffer insertion can be performed in a simple non-timing-driven wayby following a rule of thumb: the maximal interval between two neighboring buffers is no greaterthan certain upper bound. Similarly, we restrict the maximum load capacitance U a buffer/drivermay drive, so that sink/buffer capacitance can be incorporated. To keep the succinctness of thetile-based interval metric in [14], we discretize the load capacitance in units equivalent to thecapacitance of wire with average tile size. Thus, we can prune out all intermediate solutions withload capacitance greater than U.15
Page 4 and 5: ts(a)(b)Figure 28.3: Routing graph.
Page 6 and 7: uffer nodes. A buffer node always h
Page 8 and 9: 4.1 Tree Adjustment TechniqueAs a r
Page 10 and 11: the root of the subtree. The label
Page 12 and 13: s1s2s1s2Figure 28.11: A graph for g
Page 16 and 17: During the bottom-up process, each
Page 18 and 19: v1v1v5v6v2v4v3v4(a)(b)Figure 28.14:
Page 20 and 21: For Critical Nets, the cost impact
Page 22 and 23: candidates, which is chosen by the
Page 24 and 25: [10] S. Dechu, Z. C. Shen, and C. C

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