Buffering in the Layout Environment - Computer Engineering ...

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During the bottom-up process, each intermediate solution is characterized by a 3-tuple s(v i , c, w)in which v i is the root of the subtree, c is the discretized load capacitance seen from v i , and w isthe accumulated congestion cost. A solution can be pruned if both its c and w are no better thananother one in the solution set associated with the same node v i .Starting from the leaf nodes, candidate solutions are generated and propagated toward thesource in a bottom-up manner. Before we propagate candidate solutions from node v i to its parentnode v j , we first find both plate P(v i ) and plate P(v j ) and define a bounding box which is theminimum sized array of tiles covering both P(v i ) and P(v j ). Then we propagate all the candidatesolutions from each tile of P(v i ) to each tile of P(v j ) within this bounding box. Since the Steinernodes are more likely to be buffer sites due to the demand on decoupling non-critical branch loadfrom the critical path, allowing Steiner nodes to be moved to less congested area is especially important.Moreover, such move is a part of a candidate solution, and therefore the move will becommitted only when its corresponding candidate solution is finally selected at the driver. Thus,the tree adjustment is dynamically generated and selected according to the request of the finalminimal congestion cost solution.5.2.2 Hybrid Approach for Tree AdjustmentAlthough the stage of plate based tree adjustment effectively improve the layout congestion issue,there are several techniques [12] to improve the computational efficiency. Actually, the runtimebottleneck is due to the fact that buffering solution has to be searched along with node-to-node 1paths in a two-dimensional plane since low congestion paths have to be found at where the buffersare needed.If we can predict where buffers are needed in advance, then we can merely focus on searchinglow congestion paths and the number of factors to be considered can be further reduced to one. Ifwe diagnose the mechanism on how buffer insertion improves interconnect timing performance,it can be broken down into two parts: (1) regenerating signal level to increase driving capability1 The node may be the source node, a sink node or a Steiner node of degree greater than two. Thus, degree-2 Steinernodes are not included here.16
for long wires and (2) shielding capacitive load at non-critical branches from the timing criticalpath. In a Steiner tree, buffers that play the first role are along a node-to-node path while buffersfor the second purpose are normally close to a branching Steiner node. The majority of bufferinsertion algorithms such as van Ginneken’s algorithm are dynamic programming based and havebeen proved to be very effective for both purposes. However, optimal buffer solutions along anode-to-node path can be found analytically [15,16]. This fact suggests that we may have a hybridapproach in which buffers along paths are placed according to the closed form solutions while thebuffers at Steiner nodes are still solved by dynamic programming, i.e., analytical buffered pathsolutions replace both the wire segmenting [15] and candidate solution generations at segmentingpoints in the bottom-up dynamic programming framework. Computing candidate buffered pathsanalytically is faster than applying dynamic programming, which makes this hybrid approach moreefficient than the purely dynamic programming scheme.It is also suggested in [12] that the plate should be selected as a set of nearby tiles with the leastcongestion because only the nearby tiles with relatively low buffer placement or routing congestioncost worth considering to be the alternative Steiner node. In fact, if there exists a tile with highcongestion cost in the plate, it will never be used as the new Steiner node.Instead of using a length based buffer insertion, the algorithm uses analytical formula for bufferinsertion which is separated from the minimum congestion cost path search process. If given thedriver resistance, sink loading capacitance and buffer resistance/capacitance/intrinsic delay, theoptimal number of buffers and corresponding placement locations can be found with the equations[15], which are previously described in Section 2.1 of Chapter 26.We explain our buffered path routing technique by an example. For the thickened path inFigure 28.14(a), if we know the driving resistance at v 1 and load capacitance at v 4 , we may obtainthe optimal buffer positions at v 2 and v 3 . However, if we connect v 1 and v 4 in a two-dimensionalplane, there are many alternative paths between them and the optimal buffer locations form rowsalong diagonal directions. The tiles for the optimal buffer locations are shaded in Figure 28.14(a).Therefore, if we connect v 1 and v 4 with any monotone path and insert a buffer whenever this path17
Page 4 and 5: ts(a)(b)Figure 28.3: Routing graph.
Page 6 and 7: uffer nodes. A buffer node always h
Page 8 and 9: 4.1 Tree Adjustment TechniqueAs a r
Page 10 and 11: the root of the subtree. The label
Page 12 and 13: s1s2s1s2Figure 28.11: A graph for g
Page 14 and 15: 5.2 Plate Based Tree AdjustmentWhen
Page 18 and 19: v1v1v5v6v2v4v3v4(a)(b)Figure 28.14:
Page 20 and 21: For Critical Nets, the cost impact
Page 22 and 23: candidates, which is chosen by the
Page 24 and 25: [10] S. Dechu, Z. C. Shen, and C. C

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