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P ~ESCA l£<br />

I NPUT C2 C1 I~<br />

;;-----J<br />

D I~ECT<br />

I NPUT<br />

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C3<br />

nr 0 2<br />

l, l ,S,12,lJ,l.<br />

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110 I<br />

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Il • I I ;:00;-0<br />

I 1J II 10 I<br />

I NPUT<br />

SELEC T<br />

U"-"RESC"U<br />

00...." -DIRECT<br />

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GATE TI ME<br />

OI'l M- l SE\":..ljj5Y--'~.r~c~<br />

?~C<br />

+5V ~15<br />

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1.10<br />

110 1.,)<br />

Fig. 1. Schematic. Fo r U2, U3, U9, U10, U11, and U12, Vcc = pin 14 and ground = pin 7. No te: Two gates in U3 and two<br />

in vert ers in U9 are not used; gro und all unu sed inputs.<br />

l 57031 is described be low.<br />

It has l -Hz resol ution on<br />

d irect o r la-Hz resol ution<br />

on prescale using 'l -second<br />

gate time, or l a-Hz reso lution<br />

o n d irect an d 100-Hz<br />

resoluti on on prescale us­<br />

109 .1-seco nd gati ng. The<br />

di rect inp ut is go od <strong>to</strong> at<br />

least 50 MHz , and th e prescaled<br />

input should exceed<br />

500 MHz. The counte r has<br />

leading 0 bla nking, and, if<br />

turned o n w ith no in pu t<br />

signa l, will just d isplay a 0<br />

at the least significant digit<br />

po sition a long with the decim<br />

al po int <strong>to</strong> remind you<br />

what range yo u are on. In<br />

the direct mode, the decimal<br />

po int is placed <strong>to</strong> read<br />

in kHz; in the prescale<br />

mode, the d ispl ay is in<br />

MHz.<br />

Circuitry<br />

As can be seen in the<br />

block diagram, the l57031<br />

gre atl y simpl ifies th e circuit<br />

ry. The pr esc aler is an<br />

llC90 EC l IC wh ich<br />

di vides the input signa l by<br />

10 and o ut puts in TTL. The<br />

d irect in pu t pr eamp was<br />

taken from " The l atest in<br />

l S 7031<br />

Cou nters" by WA1UFE, in<br />

t he December, 1976, issue<br />

of 73.<br />

The input-se lect switch<br />

chooses t he source. Th is<br />

signal is gated by U3 dur ing<br />

the 0 <strong>to</strong> 9 counts of U'l . At<br />

count 10 , t he l o ad input <strong>to</strong><br />

I CO D.lTA<br />

BCD TO<br />

T S EGMENT<br />

DECODER I DRIVER<br />

Fig. 2. Block dia gram of LSI-based co unter.<br />

U6 goes low, latch ing in<br />

eac h d igit's value and displaying<br />

it, and at co unt 11,<br />

the Reset line goes low,<br />

resetting <strong>to</strong> 0 a ll the counters,<br />

both intern a l and exte r­<br />

na l. Then it beg ins <strong>to</strong> tabulat<br />

e a new value du rin g t he<br />

INP UT<br />

SEL EC T<br />

TI ME<br />

"" SEL ECT (~====::L...!~~__<br />

DIRECT<br />

IN PUT<br />

~ PAES CAL EIl<br />

73 Magazine. Oc<strong>to</strong>ber,1980 137

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